00:00 <charlottia> Honestly, I may be leading you astray! Please let me know how it goes!

00:04 <Stevetronics> Hey all! I have a very stupid question that I suspect is a "keyboard -> chair" glitch. I'm just poking around in Amaranth for the first time and working through the counter example in the docs to make sure my toolchain works. I can run the counter testbench if and only if I don't try to write a vcd output; I suspect that I have a version mismatch

00:04 <Stevetronics> somewhere because pysim is dying on a TypeError trying to find line breaks. Has anyone seen an error like this?

00:05 <charlottia> @vipqualitypost This isn't about making a new CD, but for me one easy way to get a clock going at the same speed as my platform clock when was to set `m.d.comb += spi_clk.eq(~clk)` (well `spi_cs & ~clk`). This way, our rising edge (when we're reading and changing things) is the SPI clock's falling edge.

00:06 <whitequark> Stevetronics: that sounds odd; can you post the complete error please?

00:08 <d1b2> <vipqualitypost> @chalottia thanks for the tip! that makes sense for alignment

00:09 <Stevetronics> whitequark - here's a paste of the error output: https://pastebin.com/Yg8whRb0

00:10 <whitequark> oh! can you post your source code please?

00:10 <whitequark> the one that produces the error

00:10 <Stevetronics> Yep! One sec

00:12 <d1b2> <vipqualitypost> it looks like you don't include 'w' parameter

00:12 <Stevetronics> Here's the counter itself (with changes from the example - rather than a configurable overflow number on a 16-bit counter, I just made the counter width configurable and overflow at 2^width - 1): https://pastebin.com/E9tUxx1R

00:13 <Stevetronics> And the testbench - just added a command line arg to set the width: https://pastebin.com/7BPAV299

00:13 <whitequark> and if you use just sim.run without sim.write_vcd you get an error?

00:14 <Stevetronics> nope, if I just do sim.run, it completes fine (no output, but all the asserts pass)

00:14 <whitequark> oh, I see now

00:15 <Stevetronics> Yeah - it errors when run is called in the write_vcd context

00:15 <whitequark> I see you're using Python 3.11; which Amaranth version is that?

00:15 <whitequark> for Python 3.11 you need Amaranth from git for the variable namer to work

00:15 <whitequark> there are actually two issues you're hitting; it shouldn't fail like that if it can't extract a variable name

00:16 <whitequark> both are fixed in git

00:16 <Stevetronics> aha - I grabbed the pip version ('amaranth[builtin-yosys]') about two hours ago

00:16 <whitequark> I recommend the git one; I think there's instructions for that in the docs as well

00:17 <Stevetronics> Got it - the docs are very clear, so I should be able to test in just a minute.

00:20 <Stevetronics> worked like a charm - thanks for the heads up!

17:45 <FL4SHK> any news on the implementation of the interfaces RFC?

17:45 <whitequark> expect by today or tomorrow (depending on timezone)