whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<_whitenotifier-7> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/3517a3d69116...bd7d491034b2
<_whitenotifier-7> [YoWASP/yosys] whitequark bd7d491 - Update dependencies.
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<_whitenotifier-7> [amaranth] daniestevez opened issue #717: Conditional assignment to a slice can generate invalid Verilog - https://github.com/amaranth-lang/amaranth/issues/717
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