02:19 <_whitenotifier-7> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±2] https://github.com/YoWASP/yosys/compare/1be258bcb111...8b3e887b635b

02:19 <_whitenotifier-7> [YoWASP/yosys] whitequark 8b3e887 - Update dependencies.

06:32 <_whitenotifier-7> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/8b3e887b635b...967f291944fb

06:32 <_whitenotifier-7> [YoWASP/yosys] whitequark 967f291 - Update dependencies.

12:29 <Guest97> Hello, people. Please point me to the right explanation how to add multiple modules to top level module without putting all source code in a single file. For instance I want top level module with instatiated 5 submodules and only connect i/o ports

12:33 <Guest97> after f.write(verilog.convert(top, name=f"Top_{Name}", ports= [ top.InputComponentStream, top.OutputDpStream, top.Ready ])) all submodules code exposed in a single file =\

12:45 <whitequark> currently all RTL is emitted in a single file

12:46 <Guest97> just to confirm self._anon_submodules = [] will not work?

12:47 <Guest97> nevermind, thanks for prompt response

12:47 <whitequark> anything involving access of private variables is explicitly unsupported

14:35 <Sarayan> whitequark: I wonder, wasn't the answer "use import, you're in python"?

14:45 <miek> they were asking about the generated verilog output

14:46 <Sarayan> ahhhhhh