16:02 <agg> is there an easy way to flatten generated verilog? I'm trying making a fragment and setting f.flatten=True before converting it, but no luck

16:04 <whitequark> that's an internal API, yeah

16:05 <whitequark> try using the yosys flatten pass?

16:05 <agg> can I invoke that from back.verilog?

16:11 <whitequark> not really

16:11 <whitequark> well

16:12 <whitequark> you could make a local modification

16:48 <agg> well, my very basic amaranth -> tinytapeout demo seems to work https://github.com/adamgreig/tinytapeout-prn

16:49 <whitequark> exciting :D

16:50 <agg> i've left out flattening for now since all my logic fits in one elaboratable anyway, heh

16:50 <agg> but in theory i think it wants to be flattened to avoid having to ensure all the module names are unique

16:52 <whitequark> i see

16:56 <agg> (since for tinytapeout eventually all the verilog's getting munged into one thing, apparently)