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<junon>
Is RIP-Relative mode what is used with you compile with PIE?
<junon>
err, rip-relative addressing*, not mode
<klange>
Should be. RIP-relative was a big improvement over the thunks that were used in 32-bit x86.
<junon>
I thought x86 already had EIP-relative addressing though? e.g. jmp short and whatnot. Am I misremembering?
<zid>
that's not an addressing mode
<junon>
What does addressing mode mean here, then? Just for reads/writes?
<Mutabah>
yes.
<Mutabah>
For doing memory accesses
<klange>
You want to load a library somewhere [or for PIE, an executable image]. You _could_ load it and then rewrite all the data references, but now you've trashed all of the code with writes and your bovines are now sad.
<klange>
Instead you use RIP-relative addressing. Your static data gets loaded with the code as a single segment (or two... r/w/x separation...) and the code knows where it is relative to itself and that doesn't change when you stick the lot at different addresess
<klange>
now all that code can remain cow-friendly, and because it's not doing extra function calls to extract EIP from stack frames, it's not any slower for it
<froggey>
mooo
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<junon>
ahhhhhh
<junon>
for static data, right
<junon>
neat.
<junon>
thanks klange
<zid>
lea rsi, [dll_base_addr]
<zid>
add rsi, symbol_offset
<zid>
mov eax, [rsi]
<zid>
vs. mov rsi, [rip+0x8394]
<zid>
well not dll, .o
<junon>
Oh okay I have definitely seen that.
<junon>
in some disasm output before
<junon>
also TIL NOP is actually XCHG EAX, EAX under the hood, and that AMD64 keeps it that way regardless of size prefixes.
<junon>
Why would that make a difference, though? Why not... do nothing? Is there an observable side effect to XCHG EAX,EAX that had to be preserved?
<zid>
it actually doesn't do that
<zid>
because it'd break a whole bunch of programs
<junon>
Ohhh it doesn't do that? The writing is vague
<junon>
section 2.5.7: > Without special handling in 64-bit mode, the instruction would not be a true no-operation. Therefore, in 64-bit mode the processor treats opcode 90h (the legacy XCHG EAX, EAX instruction) as a true NOP, regardless of a REX operand-size prefix.
<zid>
that's precisely what it says
<zid>
it says it DOES NOT do it, because that would *not* be a nop
<zid>
so it *has* to replace it with nop, because otherwise it'd.. clear the upper bits of rax
<junon>
Riiiiight okay.
<junon>
is that because 90h is an encoded instruction?
<junon>
there was no dedicated, true NOP?
<zid>
90 is nop
<zid>
and happens to be where xchg eax, eax *would* be
<zid>
if you looked at a little map
<junon>
Gotcha, so it was effectively NOP in x86 but because of zero extension in 64-bit mode it has side effects if treated as such, so AMD64 has special handling
<junon>
is what I'm understanding
<zid>
idk the exact encoding but you could imagine 7E: xchg rbx, rdx 7F: xchg rbx, rcx 80: nop 81: xchg rax, rdi 82: ..
<junon>
or, maybe not zero extension but truncation
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<zid>
it just takes the place of xchg rax, rax
<junon>
right
<junon>
okay
<zid>
it's just letting you know not to assume it does xchg rax, rax and people *treat* that as a nop
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<geist>
huh TIL that 90 is xchg
<geist>
didn't know that
<geist>
also to take it to the next level there are lots of ways to encode nops on x86. 90 is the 1 byte, but some of the optimization and/or programming manuals for intel and amd give you a list of suggested nops from 1 - 15 bytes
<geist>
for padding purposes if you need say a 3 byte nop use this, or 6 byte, etc
<geist>
usually it's a raw nop + some prefixes and such