#litex on 2024-05-03 — irc logs at libera.irclog.whitequark.org

2021-05-24 10:26 _florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex

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01:38 <joshua_> I am putting together an interface to an external module. it seems common to have, for instance, Pins that have Subsignals, and now I think it would be nice to pass busses around (i.e., SPI-like things internally). it seems to me like `Record`s may be the way to do this, but I can't find any refernece to `Record`s in the migen documentationn: https://m-labs.hk/migen/manual/search.html?q=record&check_keywords=yes&area=default are these in fact idiomati

01:38 <tpb> Title: Search — Migen 0.8.dev0 documentation (at m-labs.hk)

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