_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<MoeIcenowy> somlo: I think some spec specifies the first few interrupts are reserved
<MoeIcenowy> I am not sure what
<MoeIcenowy> but both Rocket and C906 reserve some
<MoeIcenowy> Rocket reserves 1
<MoeIcenowy> C906 reserves a whole 16
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<sensille> are there any efforts to implement ethercat?
<sensille> oh, ethercat seems to be specifically 100mbit/s, while my colorlight board seems to be hardwired to gbit
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<zyp> sensille, I'm planning to implement something ethercat-like
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<sensille> zyp: ethercat-like, but not compatible?
<zyp> yeah, I need something to do industrial real time comms, but I don't need it to be compatible with anything else
<zyp> also avoids having to deal with ethercat licensing
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<sensille> licensing :-(
<sensille> they make it sound like it is no problem at all
<zyp> ethercat masters can be done without licensing, but slaves are restricted, and that's where all the magic is
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