_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> bl0x_: sys4x is indeed used by the DRAM on some FPGA (Mostly Xilinx 7-Series/Ultrascale), this clock is used by the serializers/deserializers
<bl0x_> _florent_: ok, but could be turned into an option (at least for boards that have no DRAM built in), because it negatively impacts maximum sys clock.
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<_florent_> bl0x_: sys4x is only present on boards with DRAM
<bl0x_> _florent_: Then it is probably copy&paste leftover in the board file for cmod a7.
<bl0x_> _florent_: Just in case there is a PR here: https://github.com/litex-hub/litex-boards/pull/327
<david-sawatzke[m> florent: I've written a small hybrid ethernet hardware stack based on LiteETH, that can filter certain packets from the softcore and process it in hardware: https://gist.github.com/david-sawatzke/eb81a836391eff6a88fa7a1b63b8a67c
<david-sawatzke[m> It's smaller than full blown LiteETH and can share the IP & MAC, but a bit hacky in some places
<david-sawatzke[m> I don't think there's a good way to integrate this in to LiteETH, so I'll just leave it at posting it here for now
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