<josuah>
I am half-way (done, debug/validation needed) through the process of writing one very ad-hoc
<whitequark>
we'll have one upstream eventually
<josuah>
maybe the Interface() RFC would need to come in first, and then many actual interfaces can get a refactor and harmonization
<whitequark>
yes
<josuah>
and we have the chance to have amaranth code already written, which helps with seeing what kind of interfaces can be useful
<josuah>
thanks for the outlook!
<d1b2>
<zyp> when you say «something like», do you count bridges using USB instead of SPI? I've written one for LUNA that's compatible with the USB requests ValentyUSB is using
<d1b2>
<josuah_dem> This project I am using is not having USB accessible to the small (iCE40) FPGA, but to an MCU, so I will do a bit of plumbing across wishbone-serial and wishbone-spi (spibone).
<d1b2>
<josuah_dem> Although, this is good to know about it!
<josuah>
How is the funding of Amaranth organized? I mean it as an FAQ-style questions about the Amaranth project itself rather than an overly personnal question about the members.
<whitequark>
at the moment Chipflow has hired two developers (me and JF) to work on Amaranth full time
<josuah>
This is great news!
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<d1b2>
<Olivier Galibert> excellent
<cr1901>
Will the Amaranth stream interface include (or all) of the AXI Stream signals?
<cr1901>
include most (or all)*... stuff like TID/TDEST
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