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<d1b2>
<Nate> curious what happened with libresoc
<whitequark>
the project leader acted in a way not fitting someone in a leadership position
<cr1901>
Oh whoops. I upgraded my pacman packages... including paramiko to 3.x. Then I upgraded amaranth, did the "pip install -e ." dance, and... it reinstalled 2.x XD.
<cr1901>
Heads up for the intersection of ppl using pacman and using amaranth's remote functionality (all 3 of them?)
<josuah>
I guess all projects get a tint of their maintainer at times...
<josuah>
cr1901: do you now have both packages (in the system + in the local user)?
<josuah>
Q: how do one search the clock fequency of sync? I wish to have a delay in millisecond for an IR sensor, and wonder about the best way to get this going.
<josuah>
for now, I go with passing a parameter from the top module all the way down to my little NecIrDecoder(clk_freq_hz=1e6)
<josuah>
oh wait... I do have acess to platform.default_clk_frequency in here...
<josuah>
def elaborate(self, platform): <-- here
<josuah>
I am thinking... if the clock might change at runtime, so, not really possible to get an "absolute clock frequency" here
<josuah>
it depends on how the module is integrated... Well I'll keep a parameter maybe.
<josuah>
bl0x: learn-fpga-amaranth/18_mandelbrot/soc.py does the same it seems
<d1b2>
<dave berkeley> Last week I uploaded a dot graph of Stream interconnections using my Stream library. I've added nested Elaboratable objects, simply by recursing from the top module. This, combined with my Stream interconnections gives a very useful diagram. I think this idea might have wider use in Amaranth for generating documentation.
<d1b2>
<dave berkeley> note : my code to drive the ulx3s ADC worked first time, thank to the simulation tools in Amaranth.
<d1b2>
<Olivier Galibert> The tools are real nice until you hit an Instance, and then you cry because you don't have them anymore 🙂
<josuah>
dave berkeley: that looks like working very nice!
<josuah>
it feels good when you got the low-level primitives right and are able to compose them and it works
<josuah>
one of these "ah-ha!" moments
<d1b2>
<dave berkeley> I'm building up a library of Stream based components. With the ADC I was able to just set the clock freq, cpha=1 and cpol=1 and it worked. After a spending some time reading the device datasheet it is clear that it didn't require the usual initialisation codes to be sent. The AD56x8 does, which is where the StreamInit come in. You can define data to be sent to the SPI interface on startup, to initialise all the regs. You just pass
<d1b2>
an init list to the ctor.
<d1b2>
<VA3TEC-Mikek-14362> Dave! This is absolutely great! Do you have a github repo or anything? I would like to review and try and implement it on my Deca Board. (I completely understand that this a tall order & may take some time, and may not be released yet) I have recently was able to compile and load a similar project with Hans's USB to audio FPGA sound card. https://github.com/amaranth-farm/deca-usb2-audio-interface I did a quick search is this
<d1b2>
your CORDIC repo? https://github.com/DaveBerkeley/cordic I will try experimenting and understand your project more next, if that ok. Thanks! MikeK
<d1b2>
<dave berkeley> My code is all intertwined with a project at the moment. I'll extract the Streams / dot stuff and publish it.
<whitequark>
one other possibility is to coordinate with the upstream Streams development such that we don't end up with two subtly incompatible versions of Streams
<d1b2>
<dave berkeley> Happy to do that.
<whitequark>
let's do that then
<whitequark>
my timeline is that until the end of the month approximately I'm still handling an international move
<d1b2>
<dave berkeley> hope that goes well. How exciting. I will probably still publish my Streams, just so people can criticise it and give feedback. Clearly we want a single implementation in amaranth.
<whitequark>
sounds good
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<josuah>
> international move
<josuah>
that is a big event!
<josuah>
do you have to find a location where to rest at the destination?
<josuah>
Q: my FGPA is faster than my logic analyser, how do I go about slowing-it up?
<whitequark>
hm?
<josuah>
whitequark: by "international move" I thought you'd be living in a different country for long?
<whitequark>
permanently, yes
<josuah>
so you would need to plan everything ahead so it goes smoothly I suppose, unless knowing people in the destination
<josuah>
hence the "big event" :)
<whitequark>
it's more of a war refugee thing really
<whitequark>
not much time for planning, rapidly closing window of opportunity, very little funds
<josuah>
wishing you to skip all the VISA problems
<whitequark>
that part i have sorted
<whitequark>
it's more housing, banking, and healthcare that are a problem
<josuah>
I am wishing to do the best I can to help
<whitequark>
I'll be fine; it's mostly time consuming
<josuah>
thank you for going down to pointing me the page though
<josuah>
whitequark: I can live with it ofc!
<josuah>
I am also glad to check how low it can run, far from important though
<josuah>
amaranth/tests/test_hdl_cd.py has some .rename() magic, I'll figure out :)
<josuah>
it is the week-end, no rush allowed
<d1b2>
<dave berkeley> First pass at putting my Stream code into a package. It needs lots more work, but comments are welcome. https://github.com/DaveBerkeley/streams
<josuah>
maybe that code predates their introduction
<josuah>
interesting use of functions as a way of doing tasks as in Verilog or alike, I was looking for a way to do it
<josuah>
I definitely can learn from this
<josuah>
A: (to my own question) instead of trying to replace the "sync" clock domain, an introduction to addin an extra clock domain proves itself more effective
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<d1b2>
<VA3TEC-Mikek-14362> Thanks Dave! Very cool! 😁
<d1b2>
<VA3TEC-Mikek-14362> Just did a C note. And maybe next month, after that cannot guarantee. Wishing you luck. Mike from Canada.