azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<kittennbfive>
May i get back to you for my serial data sampling problem i talked about yesterday? After a lot of thinking i wonder if there is a timing issue, ie the serial_data does taker a path inside the FPGA that "needs more time" than the clock or the other way round, so sampling fails. What is the best practice for making a SerDes with an 50MHz clock at the input?
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