azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<kittennbfive>
Hi everybody! I am loosing my mind on a shift register problem using Yosys 0.42+36 (git sha1 07daf61ae, g++ 12.2.0-14 -fPIC -Os) and nextpnr-0.7-45-g2e8280a9) for Lattice ECP5. I am really bad with Verilog so i am probably doing something stupid... Maybe somebody can help? Let me explain:
<kittennbfive>
I have some serial data with a clock of about 50MHz that i want to deserialize and then process further. My ECP5 does not have hardware SerDes, but 50MHz is not too fast. However my simple shift register only gives 0xFF *but* if i output the serial data (sort of "loop trough FPGA") i can see it on the scope! And if i replace the shift register with a counter i can see data. I don't understand... Here is the code: