azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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given OUTFF seems unsupported by yosys+nextpnr on ecp5, is it an OK workaround to use an ODDR and feed the same value to both clock edge inputs of the ODDR? would that give equivalent determinism to using OUTFF?