azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<mwk>
hmmm.
<mwk>
any idea on how to easily obtain an xc9500 (not xc9500xl) devboard?
<mwk>
I'm trying to RE the bitstream format and found one incredibly annoying bit where the behavior makes no sense and I'd really want to just test it directly on hw...
<mwk>
(that + actually the same question for XPLA3)
<gurki>
why the effort spent on re an obsolete part?
<gurki>
(no offense, just curious)
<mwk>
I was bored and decided to reverse engineer xilinx CPLDs
<mwk>
I'm pretty much almost done, too
<gurki>
appears like theres a few devboards on ebay
<mwk>
... huh, there actually is a devboard
<mwk>
what does "unassembled" mean
<mwk>
ah screw it, I'll just buy it
<mwk>
still
<mwk>
no such luck for xpla3
<mwk>
also, lol, devboard with socketed CPLD
<mwk>
those were the times
<mwk>
well then, another devboard has been ordered
<mwk>
still need to figure out what to do about the XPLA3, though that one is less problematic
<mwk>
(as in, I'm missing two bits per macrocell but at this point I'm reasonably sure they're simply never used by ISE and can be safely left alone)
<mwk>
oh. I actually think I may know what that weird bit does. sigh.
<mwk>
right. so turns out the XC9500 devices have internal tristate buses that are not mentioned in the datasheet, but ISE will use them just fine given the usual verilog patterns.
<mwk>
and the weird bit decides if the tristate control stuff applies to the output pad driver or to the internal tristate buffer
<mwk>
... maybe I should've thought of that before deciding to order the devboard; oh well
<mwk>
and *that* little detail explains everything