azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<sensille> does ghdl support internal tri-state?
<sensille> tyring to use ghdl for vhdl->verilog conversion (standalone)
<sensille> ISE just synthesizes internal tri-state busses as muxes
<josuah> everything I was told about internal signals is to avoid tri-state in any language
<josuah> and use separate input and output for bus
<josuah> was the aim to reduce the wire count?
<sensille> my aim is to bring an existing design to life on lattice
<sensille> with a 20 year history (not mine)
<Forty-Bot> afaik lattice fpgas don't have internal tri-state busses
<sensille> yeah, i think the spartan6 neither, but ISE synthesizes it to muxes