azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<kittennbfive> Hi, question about Yosys: Does it still not support parameter real? I have a line like "parameter tCLK = 6.66;" and Yosys (build a few days ago from git-master) complains "ERROR: Parameter `\tCLK' with non-constant value!". I don't understand...
<kittennbfive> command used: yosys -p "read_verilog -pwires test.v fpga.v; synth_ecp5 -json out.json -top fpga"
<freemint> I am failing to compare an unsigned integer generated in a linear congruential generator to a threshhold and my googlefoo ran out. Code: https://pastebin.com/qzwc4c87 . I am using this tool chain https://github.com/im-tomu/fomu-toolchain/releases/tag/v1.6 baed on open source tools. I would really appreciate an explanation what i am doing wrong which makes me more able to solve such simple problems myself in the future.
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