azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
Degi_ has joined ##openfpga
Degi has quit [Ping timeout: 250 seconds]
Degi_ is now known as Degi
<sensille>
newer yosys made it worse, too
<sensille>
starting from 20220519 yosys-abc fails with return code 134. yosys still completes, but timing fails
<sensille>
without -abc9 freq. goes down from 60 to 39mhz from 20220518 to 20220519
<sensille>
(while using nextpnr from 20220407)
<gatecat>
so, the nextpnr side definitely looks like a regression in the split-slice stuff. if you are able to provide the json & lpf then I can have a look into it although I can't make any immediate promises of fix timeframe without knowing where the problem is
<sensille>
timeframe is not a problem as i currently have a running toolchain thanks to oss-cad-suite. but it would be nice to not be stuck on that version forever :)
<gatecat>
thanks!
<sensille>
in yosys i see something with "memory_libmap pass" on that day
<gatecat>
in that case I would definitely be double checking if the "-no-rw-check" flag with yosys affects anything
<sensille>
"Unknown option or option in arguments."
<sensille>
with 20220519, trying current
<sensille>
no, it doesn't do anything significant
<gatecat>
interesting, that's the first libmap regression I've seen not fixed by that (unfortunately I also don't know enough to help more...)