azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<tnt>
Is there an OSS project to use the xilinx platform cable to load a bitstream in a Zynq ultrascale ?
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<mxshift>
I thought Zynq had to load the bitstream via the ARM core
<implr>
idk about ultrascale, on 7000 if you connect the jtag you can (mostly) ignore the arm and treat the PL like a standalone fpga
<implr>
(mostly, because the arm config registers control your PLLs)
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<tnt>
mxshift: you can, but you don't have to.
<tnt>
I ended up installing Vivado Lab Edition on the remote machine ...
<tnt>
And yeah, very annoyingly this board doesn't have any decent clock input to the PL pins :/
<mxshift>
if it can be programmed like a normal ultrascale, OpenOCD should work
<tnt>
But does OpenOCD support the Xilinx platform cable ?
<mxshift>
hmm. I was pretty sure it did but looking at their source repo, I only see Altera byteblaster, Xilinx Parallel III, and Digilent's various cables
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<implr>
tnt: vivado would also generate a ps7_init.tcl which would make the ps config register pokes over the same jtag, so you can get your clocks that way
<tnt>
implr: heh, bitstream is generated from litex ... not sure it can do that.
<implr>
ah, hum, make an empty project, with whatever pl design and the ps block configured you want, then take that file from there
<implr>
and ignore the bitstream part
<implr>
*configured the way you want
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