whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Zevv> I find that ordering of code sometimes has quite some impact on synthesis area, although the behavior of the code should be the same. Compare https://zevv.nl/div/1.txt and https://zevv.nl/div/2.txt
<Zevv> If I switch around the two `case` blocks, I end up with 32 more LC's on my ice40
<Zevv> am I missing something essential here?
<tnt> well yeah ... in 1.txt the `addr` will always be 0.
<tnt> when evaluating the first case.
<Zevv> eum gimme a sec
<Zevv> oh right that makes me feel pretty stupid
<Zevv> my unit tests even fail
<Zevv> sorry for the noise, thanks!
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