ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<whitequark> I'm not sure if you can do post-synthesis Xilinx simulation with CXXRTL
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<Guest65> Hola folks
<Guest65> I was looking into variable RISCV_FORMAL
<Guest65> in picorv32.
<Guest65> What does it do? If I want to instantiate picorv for using it with Native Memory Interface, do I have to instantiate pcpi, lookahead, vars?
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<singham> RISCV_FORMAL question still remains. I'm on pc now
<singham> Kindly let me know how to instantiate picorv32 for native memory interface. In case RISCV_FORMAL is an optional variable, please let me know that too
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<tnt> RISCV_FORMAL is used only for formal verification testing, you don't have to worry about it.
<singham> So how do I instantiate it? Will just the variables of native memory work?
<singham> picorv32 core (.clk (clk), .resetn (resetn), .trap (trap ), .mem_valid(mem_valid), .mem_addr (mem_addr ), .mem_wdata(mem_wdata), .mem_wstrb(mem_wstrb), .mem_instr(mem_instr), .mem_ready(mem_ready), .mem_rdata(mem_rdata))
<singham> Like this above?
<singham> Or do I have to add pcpi and trace vars too?
<singham> tnt: Wow! Thank you so much....
* singham will be here later
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<foxfromabyss> Sorry, i think i wasn't precise enough. with `synth_xilinx -flatten` I get  "External blackbox cell `IBUF' is not marked as a CXXRTL blackbox." but I am not sure why it's external. Removing `synth_xilinx -flatten` yields "ERROR: Unknown cell `BUFGCE'". Sorry for the confusion and poor wording. I feel like i am holding it wrong but i can't figure
<foxfromabyss> out what exactly I am doing wrong  : /
<foxfromabyss> scratch that, i think i figured it out. Thanks!
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