ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<Sarayan> Hi, yosys oss does not have vhdl?
<tnt> Not natively.
<tnt> There is a GHDL plugin that allows VHDL input.
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<ikskuh> tnt: does that mean i could make projects that mix VHDL and Verilog?
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<xiretza[m]> yes
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<ikskuh> that is pretty cool
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<whitequark> you could even mix VHDL, Verilog and Amaranth, with any of them anywhere in the hierarchy
<whitequark> (any HDL that supports the Yosys RPC protocol, really)
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<ikskuh> uuh, sounds nice
<ikskuh> is there a HDL somewhere between Verilog and VHDL?
<ikskuh> i honestly like the syntax of verilog, but it's way too lax
<corecode> regarding types?
<corecode> i wanted to get into formal verification, but i don't know how to start
<ikskuh> yeah, at least some type checking would be nice
<ikskuh> and a modern module management
<corecode> systemverilog?
<bjorkintosh> corecode, from the beginning.
<corecode> not supported in the free version tho
<bjorkintosh> that's usually a good place.
<corecode> bjorkintosh: yet here we are
<bjorkintosh> Logic.
<ikskuh> i am confuse now
<corecode> bjorkintosh: my brain is just not trained to think in explicit (temporal) invariants
<corecode> ikskuh: about?
<ikskuh> the last 6 lines of text before that message
<bjorkintosh> corecode, maybe chatgpt will do all the hard verification work and we'll just sit back and watch.
<ikskuh> lol
<bjorkintosh> corecode, seriously. try it and see.
<corecode> bjorkintosh: you mean try chatgpt?
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<bjorkintosh> sure.
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<corecode> i don't even know how to start
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<bjorkintosh> where have I heard that before?
<bjorkintosh> <corecode> i wanted to get into formal verification, but i don't know how to start
<corecode> yes, it's the same issue
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