ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<bl0x_> btw, is there any experience with the Cologne Chip FPGAs from Germany? They seem to use Yosys in their standard toolchain + a custom PnR.
<trabucayre> last toolchain is a bit more stable
<tnt> bl0x_: no experience yet, but according to UPS I should have a dev kit in a few hours :)
<bl0x_> tnt: what is the price for one? I requested a quote but no answer yet.
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<tnt> bl0x_: I have no idea sorry :/
<tnt> Ah nm, it's 234 EUR
<tnt> it's on digikey.
<tnt> search for CCGM1A1-E1-31B
<trabucayre> bl0x_: I have to finish with https://github.com/YosysHQ/yosys/pull/3321 :-/
<trabucayre> tnt: you must replace ALL jumpers to avoid regulators issue
<tnt> trabucayre: replace all jumpers ?
<trabucayre> to avoid reboot
<bl0x_> tnt: thanks
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<dormito> Hmm. I just noticed that a recent (last ~ 14 days) sby (symbiyosys) seems to now be driving yosys incorrectly: get complaints that "formalff -setundef -clk2ff -ff2anyinit -hierarchy" has an unknown option.
<jix_> dormito: it should work with the latest yosys
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<foxfromabyss> hi! I am currently using yosys to get systemverilog files elaborated and then fed into nextpnr for a xilinx board. That part works, even though I am using a couple of vendor specific primitives. However, as part of the design flow, I wanted to get `write_cxxrtl` to run. It sadly fails with `External blackbox cell `BUFGCE' is not marked as a CXXRTL
<foxfromabyss> blackbox.`. I am at a loss as to how to configure a specific module to be blackboxed. I've tried to include the BUFGCE unisim source file from the vivado libs, but that didn't work. I am honestly at a loss at this stage and would appreciate any sort of pointers/directions :)
<foxfromabyss> here's how I am invoking it: `yosys -q -L ${BUILDDIR}/yosys.log -m systemverilog -p "read_systemverilog -defer ${SOURCES}; read_systemverilog -link; hierarchy -top rvlab_fpga_top; synth_xilinx; write_cxxrtl test.cpp"`
<foxfromabyss> here's how I am invoking it: `yosys -q -L ${BUILDDIR}/yosys.log -m systemverilog -p "read_systemverilog -defer ${SOURCES}; read_systemverilog -link; hierarchy -top fpga_top; synth_xilinx; write_cxxrtl test.cpp"`
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