ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<DiffieHellman> This may be the wrong place, but here I go anyway. I'm trying to do UART loopback (i.e. type in GNU screen and the character is displayed). I'm using 9600 baud and no parity bit. I did get it working, but garbage output for some characters is returned if I type fast. For the rx/tx input/output loop, I used 19200Hz, but different clock rates have all the same issues. I also tried making a FIFO
<DiffieHellman> buffer, but I get the same thing. Any suggestions?
<sorear> insufficient stop bits?
<tnt> huh ... what uart core are you using ?
<DiffieHellman> I just used 1 stop bit, but I guess I could make it 2. tx should just work as tx only, works fine at high speeds with 0 errors, but I guess it isn't.
<DiffieHellman> tnt: I'm not using an UART core, just some magic I wrote up myself.
<tnt> "some magic" ? I'm not sure what you expect as answer ... without seeing the logic, the most insight I can provide is "your code is buggy" ...
<DiffieHellman> I'll upload it to my git so you can see it I guess.
<tnt> did you simulate it ?
<DiffieHellman> Simulation is no fun, I always just go straight to hardware. I made the previous version pass a linter and that's about it.
<tnt> ok, well I'll leave you have fun then.
<tnt> wouldn't want to spoil it.
<tnt> whitequark: I'm a bit lost in the templates when trying to implement the blackbox. Do you see anything wrong with :
<tnt> this->p_mem__rdata.set<uint32_t>( this->mem[this->p_mem__addr.get<uint32_t>()] );
<tnt> (I mean, it doesn't build so it's obviously wrong, but the error "error: use 'template' keyword to treat 'get' as a dependent template name" means nothing to me)
<tnt> Ok ... nm ... apparently it's:
<tnt> this->p_mem__rdata.template set<uint32_t>( this->mem[this->p_mem__addr.template get<uint32_t>()] );
<tnt> I have never seen 'template' used in the middle of an expression like that in my life ...
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<tnt> So ... I was hoping this would implement a sync memory : https://pastebin.com/cyHubejG
<tpb> Title: template<size_t AW>boolbb_p_memsim__data_impl<AW>::eval(){ if (this-> - Pastebin.com (at pastebin.com)
<tnt> But it doesn't look like it does. The reads look async with the data changing as soon as the address is changing.
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<fmahnke> Come someone recommend a channel or forum to get beginner help with the ice40 breakout boards? Not necessarily yosys related.
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<tnt> Mmm, look like cxxrtl is also not simulating SB_RAM40_4KNW properly. SB_RAM40_4K seems to work, but not the variant with inverted write clock.
<whitequark> yes, multiclock designs with CXXRTL do not currently entirely work
<whitequark> this is a known issue I'm looking into recently
<whitequark> <tnt "So ... I was hoping this would i"> could you file an MCVE on the Yosys bug tracker?
<tnt> whitequark: you mean the blackbox snipped I pasted is actually supposed to work ? I thought I had misunderstood the API or something.
<whitequark> tnt: looks reasonable to me, but it's not the complete design
<tnt> yeah, I'll try to make a minimal example
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<whitequark> thank you
<tnt> Ok, well, I see why it doesn't work ... but ... not what the right fix is.
<whitequark> yeah?
<tpb> Title: cell_p_dut__I->p_clk = p_clk.curr; cell_p_dut__I->p_mem__we = p_mem__ - Pastebin.com (at pastebin.com)
<whitequark> oh yes, this is a race
<tnt> For the "posedge" detection thing to work, the eval should be between after the p_clk assignement and the "input" assignements.
<whitequark> in zero physical time
<whitequark> okay, that's... yeah, that's a non-trivial problem
<tnt> Ok, that's unfortunate. I worked around it for now by "sampling" (i.e. doing the get()) on negative edge, and then using that value when doing the lookup and set() on the positive edge. Not ideal but will have to do for now.
<whitequark> yes, that works
<whitequark> once I have the redesign of the scheduler finished, it will work properly
<whitequark> that is long overdue anyway
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