<anuejn>
gatecat: is there a way to force a net in nextpnr-ecp5 to use global roting?
<anuejn>
(I have a design that uses global routing for a net when only a sub-part is synthesized but does not use global routing when I enable all functionality; the sub part works, the full design not)
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<gatecat>
anuejn: yeah, if you add a DCCA buffer then everything on the output side will use global routing
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<anuejn>
gatecat: thanks.
<anuejn>
well, I think my question was inaccurate
<anuejn>
Is there a way to force a signal to go with *minimal routing* to the clock tree
<anuejn>
more specifically a signal from a pin that is not clock capable
<gatecat>
no, there are some heuristics to try and do this but they must not be working in this case
<anuejn>
ah I see
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