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<qschulz>
marex: I get unaligned fdt address in TF-A on my Rockchip PX30 module which breaks console support in TF-A
<qschulz>
RK3399 DT support for TF-A seems to be broken too but from at least v2.6 (can't find the magic sequence at the address but I haven't started to debug it really)
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<yollom>
I'm trying to update from a vendor U-Boot based on v2018.1. I can copy the dts and defconfig to v2020.1, but with v2021.1 I run into issues
<yollom>
With v2021.1 I see an "initcall sequence failed" and v2022.1 I don't see any console output
<yollom>
It looks like a lot of things have changed over the years around Zynq
<yollom>
And I'm using FSBL rather than SPL
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<marex>
yollom: please ask xilinx for help with their downstream fork
<marex>
qschulz: does u-boot pass DT to ATF in your case ?
<qschulz>
marex: on my Rockchip PX30 module, yes
<qschulz>
since it's the default UART in TF-A for PX30 is not the one we use
<qschulz>
-it's
<marex>
qschulz: odd, and the DT is really not 8-byte aligned ?
<marex>
qschulz: I vaguely recall patches which did all this 8 byte alignment dance
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<qschulz>
the base address isn't, no
<qschulz>
it's 4-byte aligned
<yollom>
marex: Yah, just a lot nicer to chat in IRC then their forum
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<yollom>
I figured out the issue. Pins are sampled on power on and stored in a register, then U-Boot uses that register to get the location of the env
<yollom>
Which is super weird because just because the boot mode is set for a device doesn't mean the env is also there
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<Tartarus>
qschulz: I guess the question is who or what tool isn't properly aligning the DT, since it must be 8 byte
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<qschulz>
Tartarus: I haven't dug much in how and what U-Boot passes to TF-A, but it seems to be the RAM address of the FDT from the u-boot.itb?
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<qschulz>
TF-A does no manipulation on the fdt address upon receival AFAICT
<Tartarus>
Yeah, it could well be our tooling not enforcing the alignment
<qschulz>
the address is 4-byte aligned though, but no idea if it was by chance the time I checked or if it's 100% reproducible
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<Tartarus>
But it must be 8 byte aligned, per spec
<qschulz>
yes, and it is now enforced in master TF-A/dtc
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<qschulz>
Tartarus: marex: nvm the address passed by U-Boot seems to be 8-byte aligned and TF-A is doing something shady
<qschulz>
sorry for the noise (was wrongly printing the address :/)
<qschulz>
actually not incorrectly, just too late, TF-A does indeed manipulate the memory address given by U-Boot :)
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