Tartarus changed the topic of #u-boot to: SOURCE MOVED TO https://source.denx.de/u-boot/u-boot.git / U-Boot v2022.04, v2022.07-rc2 are OUT / Merge Window is CLOSED / Release v2022.07 is scheduled for 4 July 2022 / http://www.denx.de/wiki/U-Boot / Channel archives at https://libera.irclog.whitequark.org/u-boot
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<jelle> does anyone know how to develop on fedora's u-boot on the rpi? I've build uboot-images-armv8 but replacing the rpi3-u-boot.bin with /usr/share/uboot/rpi_3/u-boot.bin did not lead to a succesful boot so I'm wondering if I'm missing something
<jelle> I also rather build from u-boot.git
<fALSO> dont know how the boot sequence works on the rpi, but normally (at least on the boards i have, the u-boot resulting file needs to be flashed to a specific place on the card)
<fALSO> dont know if the in rpi you just put it somewhere ;-P
<jelle> that's not the case on the RPI
<fALSO> ahhh OK
<fALSO> =)
<jelle> allwinner is easier in that regard yes :)
<fALSO> i've just played with orange pi's and rockpr64
<jelle> as far as I understand the broadcom bootloader loads u-boot which sets up an EFI env
<jelle> well hmm it did start, just did not boot, should figure out the error message. I'm now wondering it trusted firmware
<fALSO> dont know if this is "updated"
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<jelle> kernel=rpi3-u-boot.bin aha yeah
<jelle> seems accurate
<fALSO> :-)
<jelle> actually seems my issue is more that the build u-boot is bork :)
<jelle> "card did not respond to voltage select! -110
<fALSO> ahhhhhhhh
<fALSO> thats "better"
<fALSO> probably bad power supply or the card is dying hehe
<jelle> no
<jelle> if I cp the old u-boot back it works fine
<jelle> so could just be that I booted a faulty u-boot
<mps> some time ago I wrote this for alpine linux https://arvanta.net/alpine/mailine-rpizw/
<mps> it is for Rpi zero, only rpi I ever had
<monstr> Hi, (trini,pbroginson,) is there any need to do something around SLS? There was v6 in the kernel https://lore.kernel.org/r/20210305005327.405365-1-jiancai@google.com It wasn't applied as a solution. Was there any discussion/decision about it?
<jelle> fALSO: mps ok this is fun, my own cross compiled u-boot seems to work \o/
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<hanetzer> so, under most normal circumstances, every patch/commit should at least be compilable individually, but what about during soc bringup?
<fALSO> jelle, =)))))
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<rfs613> hanetzer: git bisect doesn't know about soc bringup, so you still want to ensure it builds with each successive commit. Your soc may not boot or function, but the rest of the code should not be affected.
<rfs613> at least that's my $0.02... I am not a maintainer and I can't speak for them ;-)
<Tartarus> monstr: Oh "fun". Yeah, I have no idea and I would hope / assume someone from Linaro or Arm would be posting something.
<hanetzer> rfs613: blerg. because I can't build soc without a board file and whatnot.
<j`ey> hanetzer: can't you introduce a board file first, that builds, but doesnt work, and then add the drivers / config etc
<hanetzer> and that needs a dts, and those need clock bindings things, and whatnot.
<hanetzer> because I have a whole new arch/arm/mach-hisilicion tree lmao
<monstr> Tartarus: we got that request and I also don't want to spend any time on it because that's something what ARM should be fixing.
<monstr> also that upstream discussion is not over. We added the flag for compilation to TF-A which was accepted by ARM but not sure if make sense to pass -mharden-sls=all compilation flag to all arm64 based platforms
<monstr> What should be the right way to go? I mean can you bring this up with ARM/Linaro guys to get any feedback on this?
<monstr> apalos-: Any opinion about it?
<hanetzer> screw it.
<Tartarus> monstr: First I'm hearing of the issue even
<Tartarus> apritzel: ping :)
<apalos-> monstr: I just saw that, need to go and read that thread
apalos- is now known as apalos
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<rfs613> when using DM during early boot (before reloc), how does probe ordering work? In the pre-DM method, the board.c file would make direct calls in a specific order. Trying to wrap my head around how this is supposed to work under DM.
<rfs613> i'm specifically thinking of things like clock, pinmux, and DDR initialization
<cambrian_invader> stuff like clk_get_by_name() will probe the clock driver if it hasn't been probed already
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<hanetzer> blerg... these plls accept a fbdiv of 0-4095 and similar 0-indexed values, you'd think they'd set them as bit+1
<hanetzer> and their datasheet says that the APLL has a max freq of 800mhz but the vendor code sets it to 1.1ghz lulz
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<marex> hanetzer: the +1 costs many trasistors
<cambrian_invader> the +1 is free in transistors...
<hanetzer> yeh. and so does using big endian apparently. tbh I really hate little endian. $1,337 dollars is not written $337,001
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