08:14 <Esierp> @rapzak_ i've seen your reply from yesterday with the irc logs ;) thanks for the informations.

08:14 <Esierp> I'm still trying to get the DPAuxFilter working for VCDImport - but unfortunately I fail. So far I have only tried to set the input analog interface of the DPAux to digital. Unfortunately, more probably needs to be done for this and I first have to find my way around it

08:15 <Esierp> and the digilent analog discovery board will arrive at monday. so i need to wait a few days to test the scope ;)

08:23 <azonenberg> Esierp: generally speaking most filters don't care where the data came from

08:23 <azonenberg> vcd, csv import, any supported scope, all the same

08:24 <azonenberg> that's the whole point of the unified filter graph architecture

08:24 <azonenberg> The dp aux filter appears to expect an analog input

08:24 <azonenberg> so VCD will not work because it's expecting an analog value not a digital one

08:25 <azonenberg> but any format that can store an analog value should be ok to import from

08:25 <azonenberg> the other thing to note is that it does expect a uniformly sampled input

08:25 <azonenberg> i.e. all samples at equal intervals

08:26 <azonenberg> it's probably possible to extend it to support sparse inputs too if needed

08:42 <Esierp> so maybe it would be possible to make a transformation/manipulation from the vcd to analog with sampling steps and pass it to the dpaux filter

08:42 <azonenberg> or make the dpaux filter take digital, etc. i'd need to look at the filter to see

08:42 <azonenberg> what i think is going on is that it's analog because it needs 3 possible signal states

08:43 <azonenberg> differential high, low, or zero

08:43 <azonenberg> but i could be wrong on that

08:43 <azonenberg> i either didnt write that block or it was long enoug hago i dont remember doing it :p

08:45 <Esierp> in principle, the aux protocol is only an i2c, with clock recovery or with an known sampling frequency (in most cases ~1Mhz). On HW the signal is a Differential signal. but in the FPGA it is converted to an single ended signal biDir.

08:45 <azonenberg> yes, thats the point though

08:46 <azonenberg> i think the current decode relies on the differential-zero state to find the start of a transmission

08:46 <azonenberg> and thus won't work with a purely digital signal unless you had some way to squelch it

08:46 <azonenberg> the dp aux decode iirc was based on the manchester code logic written for 10baseT which uses differential zero for squelch

08:48 <azonenberg> it assumes you are using either a diff probe or subtracting two analog measurements

08:48 <Esierp> ok, i understand.

08:48 <Esierp> When i have a little bit more time, i will try to make an filter which works only on the digial signal to decode this

08:49 <azonenberg> it might make sense to replace the current decode with that

08:49 <azonenberg> you can always turn an analog signal into a digital by thresholding

08:50 <Esierp> yes, so it can easily passed then to the digitalAuxdecoder

08:50 <azonenberg> and in the v0.x series i'm not opposed to breaking compatibility with old filters if there's a good reason

08:54 <Esierp> which module u think, it is easy to understand, how the filters are working under the hood to have an kickstart with the whole project

09:17 <azonenberg> Threshold is probably one of the simplest

09:17 <azonenberg> no gpu acceleration, very simple logic