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[scopehal] azonenberg pushed 1 commit to master [+0/-0/±2] https://git.io/JRjhj
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[scopehal] azonenberg c0a02e9 - FFTFilter / DeEmbedFilter: if clfftBakePlan fails, gracefully degrade to ffts rather than SIGABRT'ing
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[scopehal-apps] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/JRjjk
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[scopehal-apps] azonenberg 5b392c9 - Updated libscopeprotocols with graceful failure in case of clfft initialization errors. See #384.
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[scopehal-apps] azonenberg edited a comment on issue #384: ERROR: OpenCL error: clBuildProgram (-11) - https://git.io/JRjjl
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[scopehal-apps] azonenberg edited a comment on issue #384: ERROR: OpenCL error: clBuildProgram (-11) - https://git.io/JRjjl
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[scopehal-apps] ncicek commented on issue #385: ERROR: Internal compile error, error code: E_SC_NOTSUPPORTED Shader not supported by HW - https://git.io/J0fe6
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[scopehal-apps] azonenberg commented on issue #385: ERROR: Internal compile error, error code: E_SC_NOTSUPPORTED Shader not supported by HW - https://git.io/J0fvS
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[scopehal-apps] ncicek commented on issue #385: ERROR: Internal compile error, error code: E_SC_NOTSUPPORTED Shader not supported by HW - https://git.io/J0fJE
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[scopehal-apps] ncicek deleted a comment on issue #385: ERROR: Internal compile error, error code: E_SC_NOTSUPPORTED Shader not supported by HW - https://git.io/J0fJE
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[scopehal-apps] ncicek commented on issue #385: ERROR: Internal compile error, error code: E_SC_NOTSUPPORTED Shader not supported by HW - https://git.io/J0fJw
<gruetzkopf>
the DX010 does 10G breakout just fine
<gruetzkopf>
caveat: in breakout mode all four lanes of the QSFP+ port need to be at 10G or at 25G
<azonenberg>
Probably a four lane serdes macro with one tx pll
<azonenberg>
fairly common
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[scopehal-apps] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/J0fT8
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[scopehal-apps] azonenberg 3355931 - Fixed typo in error message
<gruetzkopf>
they're not too hard to get fpr 500USD in the US, either - though some may need a low-value pullup on LPCCLK
<azonenberg>
Lol
<azonenberg>
oh, they use THAT chipset
<gruetzkopf>
yes
<gruetzkopf>
mine's the fixed stepping, thankfully
<gruetzkopf>
(and was barely used in a (network) lab setting
<gruetzkopf>
and though breakout is bad for failure domain size, it's a quite cost effective even on fibre with the annoyingly expensive MPO breakout cables
<azonenberg>
Yeah
<azonenberg>
I'm keeping 10G per fiber line rate for the foreseeable future
<azonenberg>
i.e. 10Gbase-SR and 40Gbase-SR4
<azonenberg>
because this is compatible with 7 series FPGA SERDES, as well as Kintex UltraScale
<azonenberg>
To get to 28G capable SERDES you need to go to Kintex Ultrascale+ or Virtex UltraScale which are far more expensive (prices in the 4 digits minimum)
<azonenberg>
There's nothing in the hundreds of USD with 28G SERDES yet, at least from xilinx
<azonenberg>
Also because 28G is a little fast to do SI work on with my current scope
<azonenberg>
with my 16 GHz scope - which can be upgraded to 20 if I want to pay for the privilege - I'm well positioned to do SI measurements at up to the third harmonic of 10.3125 Gbps
<azonenberg>
So basically it's fast enough to more than meet my needs for the next few years, reachable by FPGAs I can afford, and I can actually debug it with hardware I have in the lab
<gruetzkopf>
nothing i'm doing exceeds 10G lane rate (well except for two loopbacks on the switch)
<gruetzkopf>
i have a lot of dual port 40G ethernet cards that cost me 8.9USD new (because they only fit certain HP servers) plus 3€ (for adapter pcb plus pcie connector) each.
<gruetzkopf>
same for the FPGAs i'm willing to affort, though i ended up on the intel side of the wall because cheap msft-propietary boards appaered new on ebay for ~70€
<azonenberg>
Also speaking of high bandwidth I'm doing fnial review on the AKL-AD3 amplifier PCB now
<azonenberg>
Ordering boards momentarily, then off to the lab to test assembly of the flex pcb for the tip
<gruetzkopf>
very nice
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[starshipraider] azonenberg pushed 3 commits to master [+22/-5/±5] https://git.io/J0fLY
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[starshipraider] azonenberg 2531099 - Added lots of probe simulations
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[starshipraider] azonenberg 4926481 - Added lots of SMA test sims
<gruetzkopf>
i may eventually aquire enough <s>excuses</s>reasons to aquire some for work
<gruetzkopf>
though until now all high-speed digital stuff i did refused to be a problem
<azonenberg>
Yeah makes sense
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<azonenberg>
AKL-AD3 amplifier board ordered
<azonenberg>
also soldered up a tip and began work on gluing it into the lower housing. Assembly of these things is going to be a pain, i may end up making some kind of custom assembly jig
<azonenberg>
you have to curve the flex just right then hold it in place while gluing it
<azonenberg>
at an awkward angle on the inside of a v-shaped cavity