02:06 <M9names[m]> <tiwalun[m]> "I think I didn't really understa..." <- oh right, riscv32[e,em,emc] are *already* tier 3 targets - @heksa added them.

02:06 <M9names[m]> but they're right at the bottom of the platform support page, which makes them hard to discover because almost the entirety of the list is in alphabetical order.

02:41 <Jubilee[m]> hey y'all

02:41 <Jubilee[m]> 9names: if you want to sort the list you can just send a PR sorting the list

02:42 <Jubilee[m]> speaking of that target

02:42 <Jubilee[m]> almindor @dkhayes117... (full message at <https://catircservices.org/_irc/v1/media/download/Ac3j4265Mdk_30AlwhVqfelosQeFyeFqGlrxaIQXB6SESNC0CXL9Kgwe2W2TuZoP3yd13rnW1KJCUvoafRmVHbq_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9lUFNnb1FqUkVha1BBcUFBRXppaXBWU1U>)

02:54 <M9names[m]> <Jubilee[m]> "9names: if you want to sort..." <- already started work on it ;)

02:55 <Jubilee[m]> nice, thank you

02:57 <Jubilee[m]> almindor romancardenas mabez rmsyn The riscv32e target was added without checking with you folks, so you officially are NOT maintainers of the riscv32e target (and thus it has a separate platform support page, etc.). I suggested there be coordination about the target so that you could be co-maintainers since I did not want anyone to be signed up for work without their consent, but that evidently did not happen yet. I would like

02:57 <Jubilee[m]> this to unhappen, since it would help get the feature requests you er, requested, merged, since then you could say "yes please merge this" about things like https://github.com/rust-lang/rust/pull/134358 without it being Kinda Weird. Could one of you send a PR in to update the target platform support pages appropriately and then have the others chime in that yes they are game for this?

03:38 <cgc17[m]> does anyone happen to know of or have an example of a button-blinky using interrupts and the nrf52833 PAC? for learning purposes i wanted to have a button press turn an LED on using an interrupt (without a HAL - again just to learn). the board i'm using is the microbit v2.

03:38 <cgc17[m]> i've been reading the data sheet and some code examples i found, but still can't quite figure out the steps to take (e.g., there's one in the Embassy book using IRQ but it's for stm32 and i'm struggling on how i would translate it over).

03:40 <cgc17[m]> and i know the embassy example uses the HAL, but i was taking a look at the "hidden" functions here to try and get pointers: https://github.com/embassy-rs/embassy/blob/main/docs/examples/layer-by-layer/blinky-irq/src/main.rs

12:55 <AlexandrosLiarok> any idea why I get a hardfault when invoking SCB::sys_reset from my stm32h745's M4 core?

13:03 <AlexandrosLiarok> .. nope it's not that it's the M4 core not having access to DTCM memory and clearing bootloader state that is stored in that region before the jump.

21:44 <tiwalun[m]> thejpster , dirbaio here is the example for Rust on the nRF54L15 VPR: https://github.com/Tiwalun/nrf54l15_vpr_example

22:07 <thejpster[m]> tiwalun: nice. I guess it would look pretty similar for the PPR?

22:10 <tiwalun[m]> They’re all based on the same core, so I think it should be pretty similar

22:12 <thejpster[m]> I like that they went "Well the Raspberry Pi PIO is neat and all, but what if we just gave you a RISC-V core"

23:55 <cbjamo[m]> I wonder if the parallax propeller's approach of "why have peripherals when you can just have more cores" will see some more attempts with tiny risc-v cores.

23:56 <JamesMunns[m]> Go all out like the GA144 :D