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<@xnorman:matrix.org> last week, maybe longer, James Munns suggested i might check into zerocopy as using postcard and my big struct was causing me to blow up my stack and segfault..
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<@xnorman:matrix.org> unfortunately, I have options in my data.. I could work around that but I do quite like option.. are there any other libs that i should check into?
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<@henrik_alser:matrix.org> Alex Norman: in what situation does the problem occur?
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<@henrik_alser:matrix.org> Can you have it statically allocated and pass around a pointer instead?
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<@henrik_alser:matrix.org> Or if itβs a transfer, do it in chunks?
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<@henrik_alser:matrix.org> frag: What are you soldering? 60W might be a little low if you're using lead free solder, also consider what tips are available and for future replacement
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<@fragadaleta:matrix.org> yeah there are 5 different tips. What's the power i should be looking at?
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<@fragadaleta:matrix.org> eldruin:matrix.org: really cool article! thanks for sharing
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<@henrik_alser:matrix.org> frag: In this price range i'd go for Yihua 939D+
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<@henrik_alser:matrix.org> Or if you're willing to spend a little more the AiXun T3A
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<@fragadaleta:matrix.org> k900:0upti.me: yeah i thought of that. Thing is that i have a project with xbee/zigbee stuff and some dongles for which some soldering might be needed. But you are right. My tasks at the moment are pretty much on the software part to flash on the chips
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<@fragadaleta:matrix.org> for the record i am looking for folks with network/comm. low level skills, Rust and paid contract π
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<@fragadaleta:matrix.org> in case there's anyone, DM me
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<@firefrommoonlight:matrix.org> Has anyone programmed Cortex-A using Rust? Any examples, guides etc? I don't have a project for it ATM, but would like to add to my toolkit
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<@adamgreig:matrix.org> and they're embedded in some Xilinx Zync FPGAs too
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<@adamgreig:matrix.org> sort of a chore though
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<@firefrommoonlight:matrix.org> The options!
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<@adamgreig:matrix.org> I'd have thought for highest performance realtime these days a chunky CM7 is probably better than an M55? stm32h7 or iMXRT1062 sort of thing
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<@firefrommoonlight:matrix.org> For M33, nRF53 and StmL5 are both well supported in Rust
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<@firefrommoonlight:matrix.org> Yea H7s are great!!
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<@firefrommoonlight:matrix.org> Looking into M55 now
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<@k900:0upti.me> adamgreig: The M55 is wider, but less deep, so probably depends on the workload?
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<@adamgreig:matrix.org> true, if you can use the new dsp it's probably good
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<@adamgreig:matrix.org> are there any high-clock-speed socs with it in yet?
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<@k900:0upti.me> It's also aarch64 which should also help a bunch if you have a smart enough compiler
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<@k900:0upti.me> adamgreig: I'm looking now and I can't find anything
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<@k900:0upti.me> But I feel like I've seen an announcement or two recently
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<@adamgreig:matrix.org> it's aarch64???
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<@k900:0upti.me> I think so
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<@xiretza:xiretza.xyz> according to wikipedia it's ARMv8.1-M, which doesn't include AArch64
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<@k900:0upti.me> OK I looked it up
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<@adamgreig:matrix.org> yea, aarch64 is part of armv8 but armv8-m is only T32 instructions I believe
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<@k900:0upti.me> It's aarch32, but with a 64-bit memory bus and 64-bit load/store
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<@k900:0upti.me> Which is ... interesting
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<@adamgreig:matrix.org> I don't think it's aarch32 either is it?
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<@adamgreig:matrix.org> cortex-m7 is also a 64 bit instruction and data bus (and armv7-m)
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<@k900:0upti.me> GCC says it supports aarch32, Clang only has t32, I am confused
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<@josfemova:matrix.org> eldruin:matrix.org: Nice, I'm currently shilling rust in the space systems lab of my Uni and this is good propaganda material haha
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<@firefrommoonlight:matrix.org> It looks like M55 has potential to be an even faster M7 replacement, but seems like the chips aren't there yet
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<@firefrommoonlight:matrix.org> And may not be for a few years
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<@jamesmunns:beeper.com> At some point I'm just gunna have to switch over to Cortex-A. Once we start hitting GHz and all the peripherals, there's probably not much left to benefit the simplicity of an MCU.
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<@dirbaio:matrix.org> low-power maybe
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<@dirbaio:matrix.org> or cost
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<@jamesmunns:beeper.com> I actually would love to see more usable Cortex A+M designs, where you can do the real time stuff on the M, and delegate all the hard UI and networking stuff up to the A.
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<@jamesmunns:beeper.com> I mean maybe, but stuff like the imxrt family aren't appreciably cheaper than a low cost A part
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<@jamesmunns:beeper.com> re: power, I'd love to see a device with split power domains that allows the M to keep running with the A full-off
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<@jamesmunns:beeper.com> I've seen a lot of heterogeneous parts like the imx7 and STM's parts, but I think they keep all of the core RAM on the same domain
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<@jamesmunns:beeper.com> and it's DDR that kills you
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<@jamesmunns:beeper.com> (idle power usage wise)
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<@dirbaio:matrix.org> reliability maybe?
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<@jamesmunns:beeper.com> I mean sure, there's always a niche for everything
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<@jamesmunns:beeper.com> But you can design reliable, non-Linux systems for Cortex-A too.
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<@jamesmunns:beeper.com> that's what all the auto OEMs do
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<@dirbaio:matrix.org> on ur minimum-viable-product attempts (first was rpi+raspbian, second was orange pi + yocto) we kept having the stuff randomly freeze/hang or drop off the network for no reason whatsoever, coming back when powercycled π€·
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<@jamesmunns:beeper.com> I mean
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<@jamesmunns:beeper.com> fair
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<@dirbaio:matrix.org> even using the hardware watchdog >_<
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<@dirbaio:matrix.org> but who knows why though. Sd cards, dodgy hardware (orange pi is crazy cost optimized), or me having no idea how to do embedded linux (yocto is crazy complex)
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<@jamesmunns:beeper.com> They make external watchdogs you can use with a FET to do a whole power domain cycle :p
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<@jamesmunns:beeper.com> Just make sure you service it with your app layer, not your OS, since it can keep going when everything is still busted
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<@dirbaio:matrix.org> yeah, I was feeding it from my app's mainloop, so it'd trigger if my app crashed or hanged
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<@jamesmunns:beeper.com> Some of them even give you warning, which you can use with an OS driver to flush disks and attempt to gracefully shut down first
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<@dirbaio:matrix.org> and still it'd completely hang sometimes. no network, no uart console π€·
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<@jamesmunns:beeper.com> Yeah, honestly if I wanted something reliable, I'd use bare-metal-but-with-allocator
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<@dirbaio:matrix.org> vs now with everything on nrf52 there's absolutely zero reliability issues
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<@jamesmunns:beeper.com> maybe set up my own flavor of `std`
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<@jamesmunns:beeper.com> like the esp32 folks do
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<@jamesmunns:beeper.com> Which again, isn't far off what the auto OEMs do, they either use a reliable RTOS, or use a hypervisor under the linux layer
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<@jamesmunns:beeper.com> Not saying your solution is wrong/bad! But bare-metal/no-alloc is a pretty uphill battle for a couple of tasks, especially networking and UI.
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<@dirbaio:matrix.org> networking? with async it's as easy as on std+threads :)
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<@k900:0upti.me> The only heterogeneous design like that I can remember is Intel's Quark
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<@k900:0upti.me> And we all know how that ended
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<@jamesmunns:beeper.com> and having a mostly-separate Cortex-M domain to act as your babysitter, with full power to kick the Cortex-A domain, would be pretty neat
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<@dirbaio:matrix.org> I do super complex networking on my products (ethernet, mobile/ppp, bluetooth, all mesh routed, with end-to-end encryption), with no std, no alloc :)
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<@jamesmunns:beeper.com> k900:0upti.me: There's quite a few in the arm world. Especially with Cortex-A + Cortex-M for commercial usage, or Cortex-A + Cortex-R for automotive/safety critical usage
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<@jamesmunns:beeper.com> dirbaio:matrix.org: Yeah, if you're dirbaio :D
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<@k900:0upti.me> No, I mean ones that can disable the big cores entirely
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<@dirbaio:matrix.org> and it's as easy as on std linux (because I've done it in the previous iterations...)
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<@jamesmunns:beeper.com> ahhh
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<@k900:0upti.me> To be fair, Intel _did_ fuck up impressively hard on that one, even by Intel side project standards
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<@dirbaio:matrix.org> jamesmunns:beeper.com: all that stuff is opensource, just sayin' :D
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<@dirbaio:matrix.org> vs on cortex-a I don't think I could've done it. On Linux I tried and failed. And custom cortex-a RTOS sounds like work for a 10+ engineer team
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<@adamgreig:matrix.org> jamesmunns:beeper.com: h7 splits ram into like 6 banks, most of which can be turned on and off separately
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<@adamgreig:matrix.org> so you can have the cm7 and its axisram and dtcm off, the cm4 on with one of its two ram banks, the backup domain bank off, then turn off the cm4, turn on the basic dma and backup ram, have the dma copy something out to a uart while both cores sleep, etc
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<@adamgreig:matrix.org> complexity++
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<@jamesmunns:beeper.com> Most of my research was on the imx7, when I thought about using it for that a couple of years back. Both CPUs were on the same vcore
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<@jamesmunns:beeper.com> but yeah, it certainly makes it simpler the more is common/locked together.
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<@adamgreig:matrix.org> wow, that's a cute module
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<@adamgreig:matrix.org> my tweezer fingers are hurting just imagining placing all those passives
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<@jamesmunns:beeper.com> I hope for their sanity it was all done with a pnp :/
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<@adamgreig:matrix.org> yea...
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<@adamgreig:matrix.org> the beaglebone stuff has something a bit like this right? the PRUs
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<@adamgreig:matrix.org> maybe they're more like the rp2040 pio
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<@firefrommoonlight:matrix.org> adamgreig: A neat thing about this is being able to use an H7 for both high perf, and low power uses
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<@adamgreig:matrix.org> yea, the range of power is frightening
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<@adamgreig:matrix.org> I think the lowest is about 20nA and the highest is like 600mA?
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<@adamgreig:matrix.org> wipes the floor of any cortex-a part for low-power stuff
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<@adamgreig:matrix.org> but even the cm7 at 500MHz is not going to do anything like as much number crunching as a newish quad-core cortex-a with neon etc
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<@ryan-summers:matrix.org> I assume you mean the H7 in the deepest sleep mode? I haven't many actual uses of those modes in reality
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<@ryan-summers:matrix.org> Because the only way to generally wake them is with external stimuli
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<@ryan-summers:matrix.org> At lowest practical power points, generally you have the 32KHz clock running or something, and I assume that's a few orders of magnitude above 20nA, but I've never measured
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<@adamgreig:matrix.org> yea, 20nA is extreme, that's running just off vbat with rtc and lse and backup ram all off
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<@adamgreig:matrix.org> lowest power where it can still wake itself up from a timer or whatever is about 2Β΅A
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<@adamgreig:matrix.org> (which I have measured on an h743)
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<@adamgreig:matrix.org> (I haven't measured the 20nA but I am a little curious, heh)
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<@dirbaio:matrix.org> wow 2uA on timer wakeup is really good!
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<@dirbaio:matrix.org> slightly better than nrf52840 (2.7uA)
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<@adamgreig:matrix.org> it in the 2-3Β΅A region depending on temperature and voltage
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<@adamgreig:matrix.org> well it climbs pretty quickly at temperature actually, don't run these things at 100C and hope for much battery life lol
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<@ryan-summers:matrix.org> That's still a lot better than I was expecting tbh
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<@ryan-summers:matrix.org> For how massive of an MCU it is
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<@adamgreig:matrix.org> yea! you don't think of it as a low-power option, like it's not an L4 or whatever
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<@adamgreig:matrix.org> but it's surprisingly decent, especially since you can do a great job of waking up briefly, storming through some numbers, then sleeping while the low-power dma does its job in the low-power ram or whatever
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<@adamgreig:matrix.org> they have some wild demos for "autonomous mode"
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<@jamesmunns:beeper.com> dI/dt on 2uA -> 600mA seems like it would make the caps pretty angery lol
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<@jamesmunns:beeper.com> I'm guessing it takes a couple steps to go from off-off to on-on, especially if you have to start some DC/DCs up
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<@adamgreig:matrix.org> yea, I think you'd wake up in run0* or whatever and have to turn on the plls, spin them up, switch up run mode, etc
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<@ryan-summers:matrix.org> Does the H7 have an internal core regulator like the nrfs?
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<@ryan-summers:matrix.org> Yes, looks like it does. Don't know if its a switcher or not
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<@adamgreig:matrix.org> I think almost all stm32s have an internal ldo to run the cpu at ~1v
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<@adamgreig:matrix.org> a few h7s also have an smps in some packages which you can use for that instead
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<@ryan-summers:matrix.org> Ah, so very similar to the nRF architecture
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<@ryan-summers:matrix.org> SMPS for efficiency gains
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<@adamgreig:matrix.org> or you can usually feed the vcore yourself, but you have to handle scaling for run mode yourself too in that case
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<@adamgreig:matrix.org> yea, on the big h7 using the built-in smps is a real efficiency saver
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<@adamgreig:matrix.org> it's also a super easy way to confuse yourself because the smps state persists through a reset, so if your firmware configures the power stuff wrong it's quite annoying
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<@ryan-summers:matrix.org> Oh really? I guess that makes sense
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<@ryan-summers:matrix.org> POR vs PUC and all that
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<@dirbaio:matrix.org> yeah it's an almost-brick π€£
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<@ryan-summers:matrix.org> Just hold it in reset while you power it up. We've all made mistakes like that ;)
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<@adamgreig:matrix.org> yea. easier said than done with most tools though
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<@adamgreig:matrix.org> they can hold it in reset while attaching debug, but not through a power cycle
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<@ryan-summers:matrix.org> There's always just holding a wire to the reset line when push comes to shove
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<@adamgreig:matrix.org> usually simplest is to reset it into the system bootloader
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<@dirbaio:matrix.org> it was really confusing because most stm32 screwups you can fix with --connect-under-reset, but not this one
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<@xnorman:matrix.org> henrik_alser:matrix.org: (a bit late in the response).. I saving/restoring to/from flash memory.. basically the entire state of my program
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<@dngrs:matrix.org> I have an interrupt based usb-uart. where/how exactly should I issue pending serial writes when those are not caused by incoming data? do I pend the interrupt then?
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<@dngrs:matrix.org> so in the case of `defmt-bbq` (logging messages over usb-uart here) I'd have to pend for every log call?
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<@jamesmunns:beeper.com> I mean, it depends on how quickly you want to flush the buffer. I *think* depending on your hardware, that interrupt might fire every 1ms or whatever automatically
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<@jamesmunns:beeper.com> not sure for the stm32 you're using
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<@jamesmunns:beeper.com> (the USB interrupt)
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<@dngrs:matrix.org> I think it's mandatory for usb to fire in regular and quite short intervals
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<@dngrs:matrix.org> in other words I probably don't need any pend to ensure messages are getting processed *at all*, it would just potentially lower the latency
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<@dngrs:matrix.org> right?
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<@jamesmunns:beeper.com> I guess? I can't remember why I did it :D
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<@dngrs:matrix.org> gonna try some LED logging
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<@jamesmunns:beeper.com> :D
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<@jamesmunns:beeper.com> 1khz might be too fast to see, but you could step down like 128:1 or so
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<@dngrs:matrix.org> yeah,
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<@dngrs:matrix.org> James Munns: ok so it seems USB polling is only required when there's stuff to process (in other words the hosts wants to set up the device or there's data incoming) and there's not automatic 1kHz or anything timer that does it. (but when you're not reacting to USB interrupts that then means you have to do a busy waiting poll). so yeah it does seem to me that when I'm using usb interrupts and only polling in...
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... them, I now do have to pend after each defmt log; at least that does fix my problem
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<@dngrs:matrix.org> that's a bit inconvenient but I guess one can write forwarding macros
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<@jamesmunns:beeper.com> You could also just set up a 10-100hz timer that boops the usb interrupt to keep things moving
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<@dngrs:matrix.org> true
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<@jamesmunns:beeper.com> Or, set a 10ms one-shot timer in each usb-poll that causes it to retrigger on a time out
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<@dngrs:matrix.org> anyway, this is all still mighty cool, I now have a device that presents itself as a usb midi controller and also logs to uart over the same usb connection
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<@jamesmunns:beeper.com> e.g. if you get usb interrupts a bunch, you keep resetting the timer, otherwise you get a 100hz idle boop to keep the queue draining
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<@dngrs:matrix.org> aye
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<@jamesmunns:beeper.com> but now I'm just getting fancy. Glad it's working!
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<@jamesmunns:beeper.com> Does this fix your "must send one byte" issue?
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<@dngrs:matrix.org> yup! I think that really only worked because I never emptied the rx buffer :D
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<@jamesmunns:beeper.com> ahhhh
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<@dngrs:matrix.org> actually since defmt only occupies tx I guess I could still use rx as a device control channel, *how cool is that*
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<@jamesmunns:beeper.com> If you don't have power concerns, I usually just poll queues like that in the idle task
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<@dngrs:matrix.org> yeah, I'll assume USB power here anyway
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<@jamesmunns:beeper.com> also: you could also wrap your TX channel in postcard to mux logging and control response
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<@jamesmunns:beeper.com> (that's what I'm going to do over rs-485)
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<@dngrs:matrix.org> pffffssht, logging *is* a control response! (but yeah, that'd be even fancier)
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<@jamesmunns:beeper.com> Since you can serde borrow, it'd be basically free too.
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<@jamesmunns:beeper.com> (on both the sending and the receiving side!)
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<@jamesmunns:beeper.com> I guess you'll incur one extra copy on serialization
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<@jamesmunns:beeper.com> but not on deserialization
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<@jamesmunns:beeper.com> and the copy will be a straight memcpy, so as fast as can be
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<@tholmie:matrix.org> Anyone have a recommendation for an embedded friendly DSP library? pretty simple things like filters and maybe an FFT. I found https://crates.io/crates/signalo but wasn't too sold on it at a cursory glance..
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<@dbrgn:matrix.coredump.ch> In the STM32L0x1 SVD file, the CNT (counter register) for LPTIM is set to `<access>read-only</access>`. Is this really the case, is this register not writable? I can't really find anything in the reference manual about counter reset...
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<@firefrommoonlight:matrix.org> I further wrapped some of it [here](https://github.com/David-OConnor/cmsis-dsp-api) to replace the pointer API with references, and remove some redundant arguments etc. Mainly for Q31 and F32 FIR and IIR
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<@firefrommoonlight:matrix.org> I didn't see that section in G0, but it's wroth a shot
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<@firefrommoonlight:matrix.org> *Looks like L0 doesn' thave `cntreset`. Maybe you can't, but they added the ability in newer versions. So in summary: Across the STM32 lineup, it appears TIMx_CNT is rw, and LPTIM_CNT is r only. On newer variants, there's a procedure to reset CNT, but maybe not on L0?
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<@dbrgn:matrix.coredump.ch> firefrommoonlight: yeah, the TIMx timers have a writable counter. I need the timer for RTIC (monotonic), so as a workaround I'll only enable it in the `reset` method, then it should start at 0 π