sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<Guest53> Hi, I'm implementing a rv32i+Zcsr for FPGA as a scholar project.
<Guest53> I've decided to have a separate ROM and RAM, harvard architecutre.
<Guest53> I'm curious about how to implement a misaligned load trap handler.
<Guest53> On the spec, if I understood correctly, mepc will contain the PC of the offending load, and mtval the address that it wanted to access.
<Guest53> Though, as I have a complete separation of instruction and data memory space, I can't read the instruction behind the mepc "address" to determine result register and width.
<Guest53> Maybe I'm missing something in the spec where the actual instruction itself is stored in a CSR?
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