<cousteau>
sorear: there used to be a # in Node, but due to the "single hash is for official channels" it had to go away
<cousteau>
so don't be sad because # is taken, be happy because it exists!
<sorear>
(free)node?
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<cousteau>
sorear: yeah I've decided to call it Node now
<jrtc27>
how about freespeechnode given it seems to be becoming a platform for die-hard free-speechers
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<cousteau>
which one? the one where if you mention a competitor you get your channel blocked without notice?
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<jrtc27>
nononono that kind of censorship is fine
<cousteau>
ah ok
<cousteau>
so the one that is not fine is whatever the former staff was doing, right?
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<jrtc27>
indeed, pesky liberals stopping people causing offence, how dare they
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<dh`>
don't let the hatespeechers define the terminology
<cousteau>
good thing the new staff would never abuse their power the way the former staff would routinely do
<jrtc27>
of course
<jrtc27>
all actions are now approved by The Board
<vagrantc>
it bends the mind a bit
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<TMM_>
my unatched is also shipping!
<TMM_>
unmatched*
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<cousteau>
is sifive the only major manufacturer of RV processors?
<sorear>
I'm not sure what you mean by "manufacturer" and "processors"
<sorear>
most RV cores are invisible
<jn>
among designers of SoC with a RISC-V main CPU, sifive isn't alone, i think Allwinner/Xuntie joined the game
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<jn>
(not completely sure about the details)
<jrtc27>
what about all the microcontroller SoCs in devices?
<jrtc27>
those are all "SoC[s] with a RISC-V main CPU"
<jn>
(xuantie, sorry)
<sorear>
most of those we don't know about because they're not standard products and not documented
<sorear>
there's gigadevice
<jrtc27>
exactly
<cousteau>
sorear: yeah I forgot what I meant too
<cousteau>
but like, "arranges the production of COTS ICs featuring RISC-V cores"
<jrtc27>
do NVIDIA GPUs count?
<jrtc27>
(don't know if they did switch to RISC-V controllers?)
<cousteau>
jn: so it's basically SiFive and now someone else joined, so 2-ish?
<cousteau>
jrtc27: woah what?
<jrtc27>
at least in the past they've wanted to have the management cores on their GPUs be RISC-V
<jrtc27>
though with their interest in Arm these days I wouldn't be surprised if that change
<jrtc27>
*d
<cousteau>
jn: in any case, that's better than one; it means the market is growing
<cousteau>
yeah didn't nvidia buy arm?
<jn>
hidden riscv microcontrollers are also in WD harddisks, as far as i've heard
<cousteau>
or the other way around, can't remember?
<jrtc27>
jn: right, but you buy a GPU for the GPU, ie a fancy processor, whereas you buy a hard disk for the disk
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<jrtc27>
I would argue "COTS ICs" includes the chip on a GPU
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<jrtc27>
as you buy it for that
<jn>
cousteau: i can't place an upper limit on the number of vendors, because i don't know the market well enough; as hinted above it depends a lot on what you count
<cousteau>
yeah ok I meant, "commercial off-the-shelf microcontrollers/microprocessors based on RISC-V"
<cousteau>
jn: that's when you start using "-ish" as a legal disclaimer
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<jn>
jrtc27: same situation, i don't buy a GPU for the management core, and the latter is riscv, not the former
<jrtc27>
honestly I'm not convinced RISC-V will take off in the western world
<jrtc27>
it doesn't have much of an advantage over Arm for most people
<cousteau>
jn: yeah it makes sense that the risc-v is the "glue core"
<cousteau>
jrtc27: dunno, there is a lot of potential for custom architectures
<jrtc27>
and even china, despite having to avoid US sanctions, has its loongarch now
<jrtc27>
well, not despite
<jrtc27>
but as in, that would be the reason to use RISC-V over Arm, yet they're doing their own thing
<jrtc27>
who wants to make a custom architecture though?
<jrtc27>
like, genuinely
<jrtc27>
who's designing it? doing the toolchain? supporting it
<jrtc27>
?
<jrtc27>
custom architectures give a terrible user experience too
<jrtc27>
for embedded uses, sure, shove your random domain-specific gunk in there
<jrtc27>
but an application-class processor going in a laptop or desktop?
<jrtc27>
it's just dead silicon
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<jrtc27>
AArch64 is not the world's greatest ISA, but it's good enough, has the backing of a major company, and is so ubiquitous that it's both widely supported by software and can be relied upon to have communities caring about it
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<cousteau>
yeah the winning point of risc-v is mostly that it got popular enough that toolchains started being built
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<cousteau>
jrtc27: isn't that loong thing just MIPS64?
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<sorear>
TwoNotes: the ABI requires 32-bit values to be kept sign extended in registers, so in 64-bit code it's much more common to use `lw` than `lwu`, even for unsigned types
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<sorear>
`lw` is also a 2-byte instruction in some cases, `lwu` is always a 4-byte instruction, don't use it unless you have to
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<TwoNotes>
I will be using it only where needed to not get the wrong result. The case I found it fetching a flag value that happened to have the sign bit set (in 32 bits) and then trying to compare it with somehting else.
<TwoNotes>
In my application, all addresses will be kept below 0x7FFFFFFF
<jrtc27>
why not compare it against a sign-extended value?
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<TwoNotes>
The code is something like, 'li' a value of FFFFFFFF into one register, then fetch a word from memory into another register and compare them with 'beq'.
* cousteau
thinks if there's a quick way to li FFFFFFFF without explicitly writing those F's
<jn>
li -1
<sorear>
TwoNotes: you could solve two problems at once by loading with `lw` and comparing it to the result of `li REG, -1` ?
<TwoNotes>
hmm. sounds possible.
<TwoNotes>
I have to go thru a lot of existing code too see what the cases are
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<cousteau>
jn: well yeah I was assuming 64 bits were involved
<jn>
ah, sorry
<TwoNotes>
See, it is not actually a -1. It is looking for the pattern of un-initialized Flash memory. On some hardware that is 00000000 and on other it is FFFFFFFF
<cousteau>
in the context of 32-bit computers, FFFFFFFF and -1 are one and the same
<cousteau>
so if you LW the 32-bit FFFFFFFF into a 64-bit reg, you get FFFFFFFFFFFFFFFF; if you LWU, you get 00000000FFFFFFFF
<cousteau>
iirc
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<TwoNotes>
As long as it looks clear what is going on. On the PDP-11 I saw a compiler generate the instuction "MOV (PC)+,4(R1)" which moves a literal 4 to 4 bytes beyond where R1 points, but does it in less memory than the more obvious "MOV #4,4(R1)". It is ok for a compiler to play such tricks but not for a human programmer.
<cousteau>
jrtc27: or... lw, addi 1, shift right 1, bnez
<cousteau>
then you check for both 0 and -1
<jrtc27>
yes
<jrtc27>
TwoNotes: that's what comments are for
<cousteau>
(which I recall TwoNotes mentioning)
<cousteau>
also yes. This is assembly, not C; there's no room for "readable code" since there's no optimization. Use comments.
<TwoNotes>
Anyway, I have to first skim through 9500 lines of AS code first looking for similar problems,
<TwoNotes>
Only 307 instances of the 'lw' instruction, most completely benign
<TwoNotes>
I agree about the comments. It is amzing how much "professional' code I have seen that has no comments at all. The comment should be the most-used feature of a language
<jrtc27>
not really
<jrtc27>
too many comments can be a thing too
<jrtc27>
especially in higher-level languages doing simple things, or where the names make it cler
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<TwoNotes>
In high-level languages, a block comment per function is plenty. Don't need explaining what N=N+1 is doing
<TwoNotes>
So many times, I do not even see ANY comment per function.
<TwoNotes>
WHat is this supposed to do? WHEN is it called? WHat assumptions does it make?
<cousteau>
TwoNotes: How to Write Unmaintainable Code encourages you to add a comment to N=N+1 explaining that it's "incrementing N", but not why
<cousteau>
and I understand your frustration at undocumented code
<cousteau>
particularly in usage
<jrtc27>
jimwilson: FYI the Freedom U740-C000 Errata link on https://www.sifive.com/boards/hifive-unmatched still has the client-side info form, despite the manual not having one any more
<palmer>
xentrac: IIUC this Allwinner chip uses the C906 core, which is the in-order core produced by the same groups as the 910 listed here (both of which are Xuantie, which is Alibaba's CPU group)
<xentrac>
as for whether risc-v will take off in the west, i think that's sort of similar to the question of whether the 8086 was going to take off in Mexico 40 years ago
<palmer>
it's all kind of confusing WRT who owns who, though
<xentrac>
it's true that the 8086 didn't have any compelling advantages over the CPUs the Mexicans were using at the time, which I think were mostly PDP-11 and whatnot
<xentrac>
but they weren't making their own chips, so...
<TwoNotes>
The Motorola 68000 was like a PDP-11. Too bad the 8086 won out
<TwoNotes>
or was that the 6800
<xentrac>
palmer: ooh, thanks, I didn't realize
<jrtc27>
palmer: T-HEAD is the group, XuanTie is the product line
<jrtc27>
I *think*
<palmer>
ya, I forgot about t-head
<palmer>
there's so many names ;)
<palmer>
but IIUC they're all closely related
<xentrac>
sounds like a rapper
<xentrac>
t-head will be sampling in la next month
<xentrac>
(joke)
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<TwoNotes>
Alibaba was working on something with a large number of cores a year or so ago
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<xentrac>
TwoNotes: see above URL
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<TwoNotes>
xentrac Yes, thats the one. 16 cores in an IoT device sounds a bit much.
<TwoNotes>
The 7.1 Coremark /MHz might be with all 16 running. Watts?
<xentrac>
important question!
<xentrac>
it doesn't seem like a lot of cores to me
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<xentrac>
heh
<xentrac>
> Alibaba launched the Pingtouge Semiconductor subsidiary last September at its Computing Conferencein Hangzhou. “Pingtouge” is a Mandarin nickname for the Honey Badger, a feisty critter celebrated across social media as the world’s most fearless creature.
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<xentrac>
they literally named the chip company "honey badger semiconductor"
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<TwoNotes>
Maybe *in support* of IoT, but not *in* IoT.
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<xentrac>
why not? how else are you going to do real-time SLAM?
<TwoNotes>
Goota get those Watts from somewhere. And cool it
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<xentrac>
two vector pipes, a couple of ALUs, dual-issue load/store
<geist>
neat
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<Sos>
0.7.1 vector extension is any good?
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<jrtc27>
it's over 2 years old, the draft spec has changed in breaking ways since then, and both major C/C++ toolchains have already stated they will never keep compatibility for draft specs
<jrtc27>
I don't know what issues there were with that version of the spec, but they existed as it's changed since then
<jrtc27>
and it's basically a waste of silicon now
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<Sos>
hmm
<Sos>
it's the same as the IGG board
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<sorear>
apparently it's compatible with current for single-byte types i.e. memcpy, strlen, strcmp
<jrtc27>
Sos: IGG board?
<jrtc27>
sorear: yeah, I saw that, mildly interesting and perhaps a fortunate coincidence
<jrtc27>
so I suppose one could retroactively add a Zvb or something that's only the subset of instructions that works across the real V and old 0.7.1 V
<Sos>
my guess is 0.7.1 is gonna stick around for some time
<jrtc27>
no, it won't
<jrtc27>
that core might
<jrtc27>
but the extension on new cores won't
<jrtc27>
not if they learn their lesson
<jrtc27>
RISC-V International and the GCC and LLVM maintainers have been extremely clear about their policy on draft extensinos
<Sos>
yeah but i guess most of the affordable chips we're gonna see are gonna be chinese companies with budget options
<jrtc27>
same goes for the Linux kernel
<Sos>
low power, low price, old spec
<Sos>
well, didn't they jsut announce a core with 0.7.1?
<sorear>
no
<sorear>
the core was announced with 0.7.1 years ago
<sorear>
there's no reason for the next cheap core to also be 0.7.1, it will likely be a different draft spec
<Sos>
ahh i thougth 'core' as in 'cpu core'
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<Sos>
yeah but the thing xentrac posted
<Sos>
an announcement of a new cpu the guys dlooing Q&A says
<Sos>
Q: plans to support RVV 1.0? A: 0.7.1 for now - when we designed, it was still at that level. We are following and working ont hat yes.
<jrtc27>
tbh I don't get how they didn't update their spec, "it was 0.7.1 two years ago when we started" isn't a great excuse
<jrtc27>
the extension isn't fundamentally changing
<jrtc27>
it's just been re-encoded and some things reworked a bit
<jrtc27>
the meat of your vector unit isn't really any different
<xentrac>
hopefully someone will fork a C/C++ toolchain that supports shipping hardware
<jrtc27>
I hope not
<jrtc27>
it's not my fault people don't listen to what they're told
<jrtc27>
if they want to implement a random draft, that's fine, just don't expect toolchains to ever support more than the RV64GC part of their core
<jrtc27>
that's all around H though, which has been basically done for ages
<xentrac>
yes
<jrtc27>
and is stalled because people want to make it wait for AIA
<jrtc27>
which is stupid
<xentrac>
I don't care if people listen to what they're told, but I do want them to have toolchains that support the hardware they have in their hands
<jrtc27>
just emulate a damn PLIC
<jrtc27>
but that's (a) privileged ISA not unprivileged ISA (b) a completely different situation
<jrtc27>
V hasn't been frozen because it's been heavily developed
<xentrac>
heavily developed but not fundamentally changing, eh?
<jrtc27>
you can't freeze a complex spec like that without getting it fully implemented in a toolchain first to work out the spec
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<jrtc27>
... you're just being awkward now
<xentrac>
heh
<jrtc27>
weird edge-cases, inconsistencies, things that make certain parts of it difficult for software to effectively use
<xentrac>
it'll be interesting to see what happens
<xentrac>
my guess is that Honey Badger Semiconductor will fork GCC or LLVM if they have to
<jrtc27>
(e.g. "this thing turns out to be common but requires $many instructions"
<jrtc27>
)
<jrtc27>
they can do what they like
<jrtc27>
nobody will use it
<jrtc27>
at least, not your distro
<jrtc27>
if you want to compile gentoo with a custom vendor toolchain that's not kept up to date then go ahead
<jrtc27>
but vendor toolchains are an awful user experience
<jrtc27>
in that you have to get it from somewhere, it's probably an old version that you're stuck with, the quality of the patches in them is usually extremely poor
<jrtc27>
and then maintainers get bug reports saying "if I build your software with this vendor toolchain it doesn't work" and it turns out the vendor broke something or didn't implement something properly
<jrtc27>
and both user and developer get pissed off
<xentrac>
well, it would be better to not have to use vendor toolchains, yeah
<jrtc27>
hence my proposal to define a standard extension that is the shared subset of the final V extension and the 0.7.1 draft spec
<xentrac>
but for that to happen, either vendors need to not implement draft extensions, or mainline toolchains need to support them
<xentrac>
your proposal might be a good way to achieve the latter
<xentrac>
although it wouldn't be adequate for objdump -d
<jrtc27>
yes, vendors need to stop implementing draft extensions that are likely subject to change unless they are prepared to take that hit and declare the silicon wasted
<jrtc27>
it would
<xentrac>
heh
<xentrac>
honey badger don't care
<jrtc27>
sure, first time round
<jrtc27>
if we cave then there will be other times round
<xentrac>
haha
<xentrac>
I'm sure that's what the bees say too
<xentrac>
I can't get over the fact that they literally named the company "Honey Badger Semiconductor"
* sorear
points at debian-loongarch
<xentrac>
I was reading Freeman Dyson's book Disturbing the Universe last night, in which he describes, among other things, the experience of designing the General Atomics TRIGA reactor, which was brought to market from initial conception in three years
<xentrac>
and I realized that the kind of hacker spirit that made that possible, which oozes out of every Feynman or Fredkin talk, is very much suppressed in the US today
<xentrac>
Dyson actually kind of spends a lot of the book complaining about "bureaucracy"
<sorear>
but people look at you funny if you come out against NEPA
<xentrac>
I have a feeling that Honey Badger Semiconductor is not run by bureaucracy but by people like Dyson
<xentrac>
well, Dyson does say he thinks it's good that we aren't able to pursue Project Orion today for environmental reasons
<xentrac>
Dyson and Fredkin have another key attribute in common
<xentrac>
they both became prestigious professors without getting a doctorate
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<xentrac>
not easy in the US at the time, but ... a lot less easy in the US today. like, I don't think it's happened in decades
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