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<enthusi>
Hi
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<enthusi>
I must be missing something simple here. How is the alignment dealt with when there are random compact 16bit instructions mixed with word-aligned RISCV code?
<geist>
as if it branches to a bad offset within another instruction?
<geist>
the bottom few bits of the instruction tell the cpu the size of the instructino, but if you branch to the middle of a larger instruction, then that's Not Good
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<geist>
basically when dealing with mixed 16/32 instructions then there's no guarantee that a 32bit instruction is 32bit aligned
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<enthusi>
geist: that was exactly my worry. So you can not branch to a label after a 16bit instruction if that carries a 32bit instr?
<enthusi>
that would be pretty bad/hard
<enthusi>
so the CPU itself can handle opcode-fetch at 16bit offsets then (even for 32bit opcodes) ?
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<geist2>
that's correct
<geist2>
basically a 16 or 32 bit instruction can be aligned on a 16 bit boundary
<rjek>
Are 32 bit integer register loads allowed to 16 bit alignment too?
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<geist2>
it doesn't affect the instruction at all
<geist2>
a 32bit instruction works precisely the same way no matter how it's aligned
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<geertu>
geist2: It does affect the instruction cache
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<geist2>
sure, but doesn't change what the instruction does
<geist2>
but sure, if it crosses a cache line or a page boundary it might take some additional time, or generate a fault
<geist2>
i think there's a 16bit nop instruction to realign things for some critical loop or whatnot, if the particular microarchitecture wants it. there's lots of cases of aligning loops and whatnot on x86
<geist2>
or, i think every 16bit instruction has a 32bit equivalent so you *could* just emit a 32bit instruction if otherwise you were going to have to just insert a nop
<sorear>
instruction fetch and data memory are two completely separate paths out to the point of unification, which is usually after the caches; a risc-v RVC core is required to support misaligned access to 32 bit instructions, but not misaligned data
<sorear>
it's not a huge amount of hardware because you're doing sequential fetches *anyway*, all you need to do is throw out the first 16 bits you get back if a jump target is 2 mod 4
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<enthusi>
sorear: but you cant branch accross a 16bit instruction to a 32bit instruction then?
<sorear>
I don't follow, taken branches generally reset the fetch machinery so it doesn't make sense to talk about branching "across" anything
<enthusi>
PC 0x0000 = 32 bit instruction with branch to LABEL
<enthusi>
PC 0x0002 16 bit compact code
<enthusi>
argh
<enthusi>
PC 0x0004 16 bit compact code
<enthusi>
LABEL
<enthusi>
PC 0x0006 normal 32 bit code at offset 6 now
<sorear>
after the branch is taken, the fetch system resets, and does a fetch from 0x0004
<sorear>
since the branch address was 6 not 4, the first 16-bit parcel is thrown away
<sorear>
the fetch from 4 is immediately followed (because no branch has been taken) by a fetch from 8, and at this point there is a complete 32-bit instruction, so it executes
<sorear>
while that's happening there is a fetch from 0xc, etc
<sorear>
there is of course a range of design space here, the fetch size doesn't have to be 4 bytes
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<enthusi>
so it kinda gets 'out of sync'?
<enthusi>
but doesnt care of course
<enthusi>
that would indeed mean (at first glance) that compact instructions have a significant impact on dye-size?
<sorear>
why would it?
<sorear>
you need 16 bits of temporary storage for the part of an instruction that overlaps between aligned words, compared to 992 bits for the main register file
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<dh`>
the simplest approach is probably to fetch from the icache in 16-bit lots
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<dh`>
the bottom few bits tells you how many more of them you need without having to decode the instruction fully
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