<Wanda[cis]>
(left bottom one being the "base", and top right being just rotated 180°)
<whitequark[cis]>
Wanda[cis]: right, that was my thinking
<whitequark[cis]>
* my thinking when asking the question
<azonenberg>
Wanda[cis]: i cant say it's *common*
<azonenberg>
but if you are able to fit two dies on a single physical mask
<azonenberg>
i see no reason why you couldn't mirror one copy of the circuit
<azonenberg>
basically a MPW with two mirror image layouts
<azonenberg>
i've never heard of that actually being done though
<Wanda[cis]>
that's like the literal largest die to date though
<Wanda[cis]>
anyway
<Wanda[cis]>
I'm wondering if the vp1902 die actually come in two enatiomers, or if the geometry database is just lying and the interposer die papers over it somehow
<azonenberg>
Good question
<azonenberg>
my gut feeling is that they're not physically mirrored
<Wanda[cis]>
so is mine
<Wanda[cis]>
it'd be strange
<azonenberg>
but there's no way they'd have connections from the right edge of the left die to the right edge of the right
<azonenberg>
just to simulate mirroring it
<Wanda[cis]>
I'm not so sure about it
<Wanda[cis]>
the SLL connections aren't concentrated on edges btw, they're kinda... spread across the whole die, I think
<Wanda[cis]>
(I haven't yet written the code to properly extract the cross-die routing, but that's what I figured from some manual poking at random wires in Vivado)
<whitequark[cis]>
i've always wondered how do Laguna connections work
<whitequark[cis]>
like on a physical level
<Wanda[cis]>
"microbumps"
<Wanda[cis]>
apparently the laguna tiles just have smaller-than usual pads on the top metal layer, which is then facing the interposer die, which... I think has through-silicon vias at these points?
<whitequark[cis]>
so they're like a bonding ball sandwich?
<Wanda[cis]>
mhm
<Wanda[cis]>
that's what the xilinx drawings imply, too
<Wanda[cis]>
and the balls are spread over the 16 or so laguna columns in the top and bottom clock regions of the die (they displace CLEM columns in these regions only)
<Wanda[cis]>
this is for ultrascale/ultrascaleplus; versal has uh. every CLB is a laguna connection point. 6 balls per CLB or so.
<Wanda[cis]>
and the actual connections between die seemed much less regular than ultrascale too
<whitequark[cis]>
wow
<Wanda[cis]>
(virtex7, otoh, is very crude and has no laguna tiles or even dedicated buffers for cross-die connections; instead they did the bare minimum modification of the interconnect tiles in top and bottom clock regions, and just fucking connected the middle-points of all long lines via super-long-lines)
<azonenberg>
i havent worked with xc7v but it makes sense it'd be the first generation of the tech
<azonenberg>
i did some work on the vu9p a while back
<Wanda[cis]>
aside of the main laguna / interconnect connections, you also have connections on the clock routing tracks
<azonenberg>
yeah i wasnt sure how htose worked
<whitequark[cis]>
Wanda[cis]: ohhh.
<azonenberg>
but i do remember having to worry about routing around the laguna tiles launching to the adjacent SLR
<Wanda[cis]>
for virtex7 it's simple: 32 balls for the 32 GCLK spines (which can be connected between die or split as desired)
<Wanda[cis]>
ultrascale has distributed clock routing (1 to 4 vertical routing tracks per column), so you just have a few extra balls here and there
<Wanda[cis]>
okay dealing with ultrascale was slow but dealing with versal makes me fantasize about ln2