<merethan>
Now microcontrollers start having more than a single CPU, life got a good bit harder.
<Haohmaru>
just use one core then
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<merethan>
lol
<merethan>
Yeah, of course. But the secure processor with the crypto features and access to the radio is CPU2.
<merethan>
So, apart from taking advantage of the nice feature of having one fast core and one slow but energy efficient one, can't really get around not using the second core.
<merethan>
I've been looking around for docs on how to address one or another AP (access port) onto the DP (debugging port) interface (JTAG? SWD?), but haven't found any concrete on it related to OpenOCD.
<Haohmaru>
no clue, others here know
<merethan>
Any of you experience with debugging multi-core things? It's a heterogeneous set too: One CM4 and one CM0+
<Haohmaru>
mr Fertser probably
<Haohmaru>
stick around, he'll show up
<merethan>
Can we summon him?
<merethan>
I got candles.
<Haohmaru>
yeah but he's probably afk since he always answers immediately
<merethan>
Haohmaru, you happen to know what timezone the elusive Mr. Fertser lives?
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<merethan>
Because I'm in GMT+1 (Amsterdam/Paris) time.
<NishanthMenon>
merethan: on assymettric multi-core debug - it is no different from single core debug - you will see different ports appear - and you can attach gdb to the port of what you'd like. I recently did a video for TI's k3 devices if you are interested in seeing how it works. https://youtu.be/n3u3QgnAvV8 (not sure it is what you are looking for)
<Haohmaru>
merethan, he's about the same timezone so just have some patience
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<Haohmaru>
let's not burry the original question with impatient conversations ;P~
<merethan>
Yes I figured such is possible. But haven't found a doc on how OpenOCD can be made to do so.
<merethan>
Also, to debug both cores simultaneously would be nice using one probe. So, somehow I need run a GDB instance per CPU, somehow using the same probe.
<NishanthMenon>
merethan: look at existing examples.. ap port and debug memory definitions usually help navigate to create the config file. there are quite the few examples out there.. mine is probably a bit complex https://github.com/openocd-org/openocd/blob/master/tcl/target/ti_k3.cfg , but I am sure you will find simpler examples there
<NishanthMenon>
merethan: that is usually what I do - a single jtag adapter, and i debug something like 8 or 9 cores (few of them in smp mode)
<merethan>
I'll try to wrap my head around it.
<merethan>
I'm also still figuring out how to combine both compile results into one .elf. For flashing, generating one .hex is probably trivial, but generating a single .elf with both programs likely requires trickery.
<merethan>
I do know that .elf files can hold binaries for multiple architectures, having the OS program loader select the correct one. Hardly anybody uses this feature of the format but for me, with two heterogeneous cores, it might be very handy.
<merethan>
Win/DOS PE's used to do this, by displaying a "This program cannot be run under DOS mode" string. That was actually a program with a single printf() put in the PE as the 16-bit binary.
<NishanthMenon>
merethan: usually we dont. typically the private peripheral views (intvecs, tcms etc) are different. we usually do two .elfs
<NishanthMenon>
more over the teams that work on each of the cores tend to have different life cycles and product priorities..
<merethan>
In here, it's all me :P
<merethan>
Time to ride my bicycle home.
* merethan
feels so Dutch today
<merethan>
I not picked a great day for that though. We have buienradar.nl for spotting rainfall, and it shown none. The drops were just too small, but those get you soaked no less with time.
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