11:53 <PaulFertser> borneoa_: hey! :) yesterday's discussion on ##stm32 highlighted a potential issue with SYSRESETREQ: https://github.com/ARM-software/CMSIS_5/issues/302 . There's also a linked issue made by someone working for NXP but explanations I could read feel unsatisfactory. My point is that /probably/ OpenOCD should treat this register the same way but it would be good to understand why exactly it might be

11:53 <PaulFertser> needed.

12:30 <borneoa_> PaulFertser: thanks for reporting it. I will have a look at it.

12:34 <PaulFertser> borneoa_: tbh, I got rather angry after reading those tickets.

14:02 <borneoa_> PaulFertser: why? Maybe I missed the point but looks like some incorrect reading of arm docs.

16:13 <borneoa_> PaulFertser: after reading, looks like a timings issue between writing in NVIC_AIRCR and the moment SW reset gets triggered. Not preserving prigroup bits can make the running FW unstable and crash before the SW reset takes effect.

16:14 <borneoa_> PaulFertser: I think we should implement the same, but maybe after 0.12.0

17:15 <PaulFertser> borneoa_: nobody really properly explained why it was needed there. So even if running FW is unstable and crashes, does it mean the target won't reset at all?

17:32 <PaulFertser> This comment seems to imply reset might fail altogether but why? https://github.com/ARMmbed/DAPLink/pull/362#issuecomment-350356905