<hanetzer>
ello. so, I've put together this config file: https://brpaste.xyz/XkMEvw; it 'seems to' work, in that I can pull information out of the soc which you'd only be able to get out of the soc (various chipid regs and so on). However if I try 'mon reset' it responds with 'hi3516dv300.a9: how to reset?', not sure where to go from there tbh. the jtag connector only has nTRST broken out
<PaulFertser>
hanetzer: then you probably need to write a Tcl handler that would use SoC's WDT to reset.
<PaulFertser>
Or another SoC-specific way. "reset-assert" handler it is I think.
<hanetzer>
got a general example of that?
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<PaulFertser>
hanetzer: atheros_ar9331.cfg where it halts the target and then does some "mww" command.
<PaulFertser>
If you have Linux sources for that target you can see how it has restart handler implemented.
<hanetzer>
its pretty simple. just a write to a reg.
<hanetzer>
PaulFertser: am I ssupposed to understand that that mww command resets the cpu?
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<PaulFertser>
hanetzer: mww is write to some memory-mapped peripheral. Should be described in the SoC manual.
<indy>
zapb__, libjaylink 0.3.0 in fedora rawhide, f37, f36 on the way
<indy>
borneoa_, PaulFertser any timeframe for 0.12 release?
<hanetzer>
PaulFertser: yeah, I know mww. I just don't know that particular register :)
<PaulFertser>
hanetzer: I suggest you check u-boot or Linux sources for your target SoC to find out the right address and value.
<PaulFertser>
indy: first RC planned for some time September iirc.
<borneoa_>
indy: yes, rc1 some time in mid September. Let's wait for people get back from vacation to ask what is pending in gerrit and valuable for the release.
<indy>
borneoa_, PaulFertser ok
<hanetzer>
PaulFertser: *I know my register*. I just didn't know the one from the ar9331 config you suggested.
<PaulFertser>
hanetzer: ah, I see. Neither did I, but I made an educated guess about the meaning :)
<zapb__>
indy, nice, thanks!
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