04:19 <trabucayre> spiOVerJtag bridges are added usually by contributors having the hardware

04:20 <trabucayre> I could do of course adds needed flavor

04:20 <trabucayre> but a vivado bitstream can't be works since the bridge as a small specific protocol

04:21 <trabucayre> building/adding a new spiOverJtag bitstream consist more or less to these modifications:

04:21 <trabucayre> https://github.com/trabucayre/openFPGALoader/commit/7bbaef0c879c9f3c30b69fb78a39a044d95d06b5

15:28 <Guest30> Thanks for the help trabucayre. I am now trying to build the new project, but I am having an issue with the edalize installation. It looks like when I try to build the files using "make" it can find the loader for the edalize package.

15:28 <Guest30> AssertionError: A loader was not found for the package edalize.

16:23 <trabucayre> I have to check: maybe my code isn't compatible with latest release :-/

16:29 <trabucayre> weird I haven't similar issue

16:30 <trabucayre> could you share modifications applied to spiOverJtag?

17:22 <Guest30> root@nvidia-desktop:/home/nvidia/openFPGALoader/spiOverJtag# git diff build.py

17:22 <Guest30> diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py

17:22 <Guest30> index a76c19c..6ccfff7 100755

17:22 <Guest30> --- a/spiOverJtag/build.py

17:22 <Guest30> +++ b/spiOverJtag/build.py

17:22 <Guest30> @@ -62,7 +62,7 @@ elif subpart == "xc6v":

17:22 <Guest30>      family = "Virtex6"

17:22 <Guest30>      tool = "ise"

17:22 <Guest30>      speed = -1

17:22 <Guest30> -elif subpart in ["xcvu", "xcku"]:

17:22 <Guest30> +elif subpart in ["xcvu", "xcku", "xcau"]:

17:22 <Guest30>      family = "Xilinx UltraScale"

17:22 <Guest30>      tool = "vivado"

17:22 <Guest30>  else:

17:22 <Guest30> @@ -112,6 +112,7 @@ if tool in ["ise", "vivado"]:

17:22 <Guest30>          "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",

17:22 <Guest30>          "xcku3p-ffva676" : "xcku3p_ffva676",

17:22 <Guest30>          "xcku5p-ffvb676" : "xcku5p_ffvb676",

17:23 <Guest30> Here are the changes I made to the build.py file. I've just been running the build.py file manually with the part number "./build.py xcau15p-ffvb676", however the edalize issue still happens with other ones, so it's likely my installation or some compatibility there.

21:43 <Guest62> Hi I am facing few issues connecting and programming a Lattice FPGA using open FPGA Loader

21:44 <Guest62> I am using a Apple Silicon M2 chip

21:46 <Guest62> While the device is reported as a USB serial device,  command "openFPGALoader --detect" does not identify the FPGA device -- the only print I see is the Jtag frequency is 6.00 MHz and invalid FPGA device

21:46 <Guest62> any help or pointers appreciated ..

21:46 <Guest62> The open FPGA was installed using homebrew