16:32 <Guest6> Good morning, have some questions about the STARTUPE3 portion of xilinx_spiOverJtag.v, I am seeing slow startup times from the SPI flash and looking to improve Configuration time

16:37 <Guest6> Looking at https://docs.xilinx.com/r/en-US/xapp1280-us-post-cnfg-flash-startupe3/STARTUPE3-Timing-Constraints

16:37 <Guest6> these values could be added to a constraints file, (.xdc) and this might improve performance

16:37 <Guest6> I am just going to dump what I have here (this is an implementation for Opal Kelly XEM8320)

16:37 <Guest6> # https://www.issi.com/WW/pdf/25LP-WP256D_128D.pdf

16:37 <Guest6> ################ PG153 for STARTUPE3 delay & its timming generation #################

16:37 <Guest6> # Tusrcclko maximum value

16:37 <Guest6> set cclk_delay 6.7

16:37 <Guest6> #### SPI device parameters - refer QSPI device datasheet & Xapp1280

16:37 <Guest6> # https://www.issi.com/WW/pdf/25LP-WP256D_128D.pdf Table 9.6

16:37 <Guest6> # https://docs.xilinx.com/r/en-US/xapp1280-us-post-cnfg-flash-startupe3/STARTUPE3-Timing-Constraints

16:37 <Guest6> # MAX Tco / Clock LOW to output valid

16:37 <Guest6> set tco_max 8

16:37 <Guest6> # MIN Tco / Output Hold Time

16:37 <Guest6> set tco_min 2

16:37 <Guest6> # SPI setup time requirement / DTR mode is 1.5?

16:37 <Guest6> set tsu 2

16:37 <Guest6> # SPI hold time requirement /DTR mode is 1.5

16:37 <Guest6> set th 2

16:37 <Guest6> set_property BITSTREAM.CONFIG.TIMER_CFG 0x00050000 [current_design]

16:39 <Guest6> Am I headed in the right direction or going the wrong way?  I see some much more simple constraints at https://docs.opalkelly.com/xem8320/flash-memory/ but after adding them did not see much difference either

18:21 <cr1901> trabucayre: >But I don't know how to access a rust libary from cpp code <-- I do, don't worry :)