02:04 <kscz> Throwing this out there to see if anyone can help - I've modified "colorlite" ( https://github.com/enjoy-digital/colorlite ) - to add in a CPU and I'm trying to get debugging over etherbone working, but I seem to be hitting a lot of stumbling blocks. My code is here - https://github.com/kscz/wyrm/tree/debug_bridge - largely contained in "wyrm.py"

02:04 <kscz> When I attempt to follow the directions here: https://github.com/enjoy-digital/litex/wiki/JTAG-GDB-Debugging-with-VexRiscv-CPU#-example - I get an exception in litex_server and it disconnects

02:06 <kscz> If anyone has time, I would be extraordinarily grateful for advice

02:12 <kscz> If it helps, I did confirm that the litex_server and etherbone are communicating by writing this simple script - https://github.com/kscz/wyrm/blob/debug_bridge/test_uart.py

02:13 <kscz> And I've confirmed that I see `memory_region,vexriscv_debug,0xf00f0000,256,io` in the `csr.csv` file

02:27 <kscz> Logs from running both the compiled OpenOCD and litex_server - https://gist.github.com/kscz/fa4371f62f5f4a9e907b7de9c989bbc4

03:42 <kscz> Well, after spending all that time to write it up, the issue is: https://github.com/enjoy-digital/litex/issues/1532