_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
Degi has quit [Ping timeout: 264 seconds]
Degi has joined #litex
spew has quit [Quit: spew]
TMM has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM has joined #litex
d_olex_ has quit [Read error: Connection reset by peer]
d_olex has joined #litex
FabM has joined #litex
FabM has joined #litex
FabM has quit [Changing host]
lxsameer has joined #litex
FabM has quit [Ping timeout: 252 seconds]
d_olex has quit [Ping timeout: 252 seconds]
FabM has joined #litex
FabM has quit [Changing host]
FabM has joined #litex
d_olex has joined #litex
ElfenKaiser has joined #litex
spew has joined #litex
TMM has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM has joined #litex
ElfenKaiser has quit [Quit: Konversation terminated!]
spew has quit [Quit: spew]
spew has joined #litex
ElfenKaiser has joined #litex
ElfenKaiser has quit [Quit: Konversation terminated!]
ElfenKaiser has joined #litex
lxsameer has quit [Ping timeout: 252 seconds]
FabM has quit [Ping timeout: 272 seconds]
Foxyloxy has quit [Read error: Connection reset by peer]
Foxyloxy has joined #litex
jersey99 has joined #litex
<jersey99> Hello hello, I have a quick question: Anybody instantiated the "Hybrid" LiteethMAC with eth_mtu set to 9k on a Xilinx FPGA? If so how did the synthesis go? I seem to hit a limit where Vivado tries to convert the SRAM into a DRAM and fails.
<jersey99> WARNING: [Synth 8-4767] Trying to implement RAM 'mem_2_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
<jersey99> Reason is one or more of the following :
<jersey99>     1: No valid read/write found for RAM.
<jersey99> ERROR: [Synth 8-3391] Unable to infer a block/distributed RAM for 'mem_2_reg' because the memory pattern used is not supported. Failed to dissolve the memory into bits because the number of bits (72000) is too large. Use 'set_param synth.elaboration.rodinMoreOptions {rt::set_parameter dissolveMemorySizeLimit 72000}' to allow the memory to be
<jersey99> dissolved into individual bits
<jersey99> Adding the FullMemoryWE doesn't seem to help the situation
jersey99 has quit [Ping timeout: 256 seconds]
spew has quit [Ping timeout: 248 seconds]
spew has joined #litex
jersey99 has joined #litex