14:17 <Pali> NishanthMenon: Hi! I would like to ask you, do you have some more details about J721E errata i2086 (PCIe - PCIe: MMA Unsupported Request (UR) or Configuration Request Retry Status (CRS) in Configuration Completion Response Packets Results in External Abort) as documented in SPRZ455?

14:18 <Pali> Or do you know somebody who has details and possible workarounds for this issue?

14:19 <Pali> I guess that it comes from PCIe IP, which is IIRC one from Cadence.

15:00 <NishanthMenon> Pali: sorry, i got into a discussion with maz on kvm and gic-v2 emulation.. checking

15:03 <NishanthMenon> Pali: as far as I can see: not-affected: AM64x_SR1.0, J721s2 SR1.0, J7200 SR1.0, J7200 SR2.0; impacted: J721e SR1.0, J721e SR1.1

15:03 <NishanthMenon> Workaround per internal notes: "PCIe user guide needs to be updated to include software workaround options for UR/AXI slave error response during enumeration" -> I dont know how that can actually be worked around in linux

15:04 <Pali> "options for UR/AXI slave error response during enumeration" --> this is something configurable by registers and is PCIe IP or SoC specific

15:06 <Pali> but I have not found which register could configure this

15:06 <NishanthMenon> Pali: copying kishon's response: "For the current version of the IP, there are no feasible workarounds. We are asking Cadence to fix this in the next version of IP by adding a bit in the Cadence Local Management register that can be configured by SW when we doesn't want to propagate slave errors."

15:06 <Pali> ah :-(

15:07 <Pali> So there is no configuration register.

15:07 <NishanthMenon> not on 1.0 and 1.1 looks like

15:08 <Pali> This is common error in more real-world PCIe implementations...

15:08 <NishanthMenon> yup.. i wonder how cdns instances on other SoCs behave..

15:09 <NishanthMenon> funny why we were the ones to catch it.. hmmm...

15:09 <Pali> Broadcom has same issues (not sure if they use Cadence) and on linux-pci are reports about those crashes.

15:10 <NishanthMenon> uggh

15:10 <Pali> Renesas too!

15:10 <Pali> And some Marvell SoCs too!

15:10 <NishanthMenon> oh gosh... TI plays janitor ;)

15:11 <Pali> I have there one Marvell SoC (Armada 3720) which has exactly same issue as J721E.

15:11 <NishanthMenon> at least looks fixed on newer SoCs .. if there is a trigger for a new SR with all level change, j721e might get it, but i doubt that..

15:12 <Pali> I think that this is common issue when HW people misunderstand how all parts on SoC works or incorrectly interpreted PCIe base specs.

15:13 <NishanthMenon> yup

15:14 <Pali> PCIe response codes could be mapped to AXI response, so HW people are doing it.

15:14 <Pali> But AXI slave error is fatal on most ARM cores.

15:14 <NishanthMenon> yep

15:15 <Pali> So the correct way is to translate PCIe error response to AXI OK response with 0xffffffff read value.

15:15 <Pali> Synopsys Designware PCIe IPs have registers for configuring these mappings.

15:16 <Pali> And nowadays Designware is most commonly used in ARM SoCs.

15:17 <Pali> So lot of new ARM SoCs are not affected by this PCIe issue.

15:26 <Pali> So you have not found any way how to do SW workaround for those aborts?

15:28 <Pali> If kishon have some idea, I would like to discuss about it as some _generic_ solution for linux kernel is really needed due to issues across more vendors.

15:42 <Pali> NishanthMenon: I see that kishon is not online so please forward above message.

15:42 <NishanthMenon> Pali: will do, but I doubt we have figured out a way to do this