20:29 <werdahias> Does anyone know what the rough status for mainline of the RK3588S is ?

20:39 <CounterPillow> https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md

20:39 <CounterPillow> same as rk3588

20:53 <werdahias> thanks :)

21:15 <minute> i always get a freeze when trying to enable pcie3x4 or pcie3x2. is this more likely to be a a problem with my hardware (icore 3588q with custom carrier) or some missing bits in https://gitlab.freedesktop.org/panfrost/linux/-/tree/panthor-v5+rk3588?ref_type=heads ?

21:15 <CounterPillow> probably some disabled clock or power domain

21:16 <CounterPillow> I don't know if mainline models the linked parent clocks properly yet

21:17 <minute> CounterPillow: hmm. i found an email thread were they had this problem with the 2.0 phy until this clock problem was fixed, but they wrote that 3.0 was working at that point https://lore.kernel.org/linux-arm-kernel/4b28da3e-9126-8409-dd9c-3899762e28bb@suse.com/T/#mdb9318844e9690f11cc6d4b8da059a178a5db344

21:19 <minute> my other theory is that i have to provide a refclk to pcie30_port1 even if i use only pcie30_port0

21:21 <minute> well, lets solder in some extra wires...

21:38 <minute> that was, indeed, the problem! boots now and now there are two controllers in lspci