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<lurchi_> How are the DDR initialization parameters for mainline U-Boot SPL determined
<lurchi_> I have two boards with rk3399, both have DDR3-800 dual channel, one has a buswidth of 16, the other has 32
<lurchi_> the proprietary rockchip loader is able to initalize both, for U-Boot two different ones seem to be required
<lurchi_> (the BW 32 is a Radxa Rock Pi N10, the other one is a STB)
<macc24> lurchi_: have you tried looking into source code?
<lurchi_> of course I have
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