17:04 <mikecoatsdotcom[> If I'm running the analyzer applet and I get a "g.applet.interface.analyzer: FIFO overrun, shutting down" is that because the voltage went too high? I'm reverse engineering a component that looks like it ties it's comms lines to 5v, then pulls low for signalling. During normal operation and shutdown I can capture VCDs just fine, but if I have the glasgow connected during the component's start up I get that error.

17:36 <Attie[m]> voltage is not the issue, it's likely too many edges in quick succession

18:02 <mikecoatsdotcom[> That makes sense. I’m seeing lots of “bounce” on the transitions I have managed to capture. Enough to throw off sigrok’s baud detector.

18:08 <Attie[m]> can you filter it at all?

18:10 <mikecoatsdotcom[> Yes, I’ve designed a custom board to sit in the middle that will let me insert any circuitry in line that I want.

18:10 <mikecoatsdotcom[> https://codeberg.org/MikeCoats/spy-break-inject

19:07 <Attie[m]> excellent!

19:07 <Attie[m]> hopefully a little RC in there will help

19:07 <Attie[m]> (unless the signals are genuinely quite fast)

19:19 <mikecoatsdotcom[> No, the signals I’ve captured so far are in the order of 1500 bps.

19:19 <mikecoatsdotcom[> I’m listening in the middle between a controller and a peripheral and if I one-shot it on my oscilloscope it looks like the same message is sent every time on start up and it looks like the response is identical too. Having a few copies of it as vcd traces would let me confirm it. Then I can start spoofing it.