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<gruetzkopf>
i've tried putting a AsyncFIFO between the io and sync domains, but now i'm getting some spurious extra bits set to 1 (the missing bytes are gone-thoug)
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<vup>
gruetzkopf: Maybe I don't get what you are going for, but why are you not using the SPI clock to sample the rx pin?
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<gruetzkopf>
no good reason except for "before i started this was the uart applet"
<vup>
The clock generated by the PLL probably has no relationship to the actual SPI clock right?
<vup>
so the clock you are sampling with and the clock that generates the input data will probably not have perfectly the same frequency and the phase between them might drift (maybe even due to temperature variation for example)
<vup>
so to make it work this way you probably want to oversample the rx pin by atleast a factor of two, but three would make data recovery easier
<vup>
But instead you could of course also just use the SPI clock input if nothing speaks against that
<gruetzkopf>
i didn't have these spurious 1-bits (most of the time in the middle of the byte) before inserting the fifo
<gruetzkopf>
so thr reason i though i could get away with this is that my SPI "packets" are exactly one byte long
<gruetzkopf>
so i'm re-syncing on every /CS -> LOW transition
<gruetzkopf>
this works well for the uart applet (which looks for the start bit instead)
<vup>
My guess would be, that the UART applet probably starts to break at 10+MHz aswell
<vup>
gruetzkopf: also can the ice40 pll actually generate 12.288MHz exactly?
<vup>
With a system clock of 48MHz you would need to multiply by 32 and then divide by 125, which the ice40 pll cannot actually do afaik
<gruetzkopf>
the uart applet works fine at 16MBit/s
<gruetzkopf>
tooling does not complain about that
<vup>
I think when setting the log level to debug you should see the frequency it actually generates
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<d1b2>
<Attie> as SPI is clocked, you can remove all of the guesswork in sample point / oversapling, and sample on the relevant edge of the clock
<d1b2>
<Attie> note also that SPI data has no relation to the CS line, aside from ignoring all inputs if CS isn't asserted... so the IDLE / START / DATA / STOP states are irelevant here(...?)
<d1b2>
<Attie> you can't use CS to transition into the DATA state and immediately start sampling the input on rx_stb - you should sample on the SPI clk line
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<d1b2>
<Attie> (i.e: SPI is very different to UART...)
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<gruetzkopf>
Attie: true in the general case, not true in this special case
<gruetzkopf>
also: i'm fairly certain that this is not the problem here, as it didn't appear over tens of megabytes of zeros before inserting the fifo
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<whitequark>
<vup "With a system clock of 48MHz you"> the UART applet does not use PLL
<vup>
whitequark: yes but the code linked by gruetzkopf
<vup>
does
<whitequark>
ah right
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<d1b2>
<Attie> @gruetzkopf ah, ok
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<d1b2>
<mbai> Hi, Is there a intro tutorial for glasgow on the web? -- I'm looking for something that just spoonfeeds the whole thing from setup to making a simple analyzer.
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