#glasgow on 2021-06-22 — irc logs at libera.irclog.whitequark.org

2021-05-20 03:31 whitequark changed the topic of #glasgow to: digital interface explorer · code https://github.com/GlasgowEmbedded/glasgow · logs https://libera.irclog.whitequark.org/glasgow · discord https://1bitsquared.com/pages/chat · production https://www.crowdsupply.com/1bitsquared/glasgow (FUNDED)

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00:03 <d1b2> <xabean> that would be awesome, thank you wq

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00:25 <d1b2> <xabean> BSR boundary scan register. That. As my evening coffee finally kicks in.

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00:28 <whitequark> yes

00:28 <whitequark> needs BSDL parsing

00:28 <whitequark> doable.

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16:06 <gruetzkopf> https://paste.ccc.ac/?b4bd5fcb7eba4e96#zGtyMV/S1hPpehkMbjZtrFMssHXPFLmoNE446+u9jlk= hm, in me making a mess of clock domain transitions, im getting this to pretty reliably to not set rx_rdy to 1 in the READY state

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16:16 <vup> I don't think the input and output signal of the FFSynchronizer should be the same Signal

16:17 <vup> also, you are rx_rdy synchronously in the READY state

16:18 <vup> which means if rx_ack is high in the same cycle you enter the READY state, rx_rdy will only be high in the IDLE state

16:18 <vup> (and the one sync cycle later be set low again because of the statement in the IDLE state)

16:18 <vup> gruetzkopf: ^

16:19 <gruetzkopf> yeah i guess i'll loop that back around (or even use rx_rdy to exit the state)

16:20 <gruetzkopf> rx_ack _is_ high all the time because i'm not saturating the USB fifo

16:20 <vup> yeah, that would mean rx_rdy will only be high on the cycle you enter the IDLE state

16:21 <vup> not sure what the expected semantics are here, but you could just set rx_rdy combinatorially?

16:22 <miek> potentially not even one cycle if there's no `sync` edge while it's in the READY state, since the fsm runs in the `io` domain?

16:23 <vup> oh whoops I completely read over that

16:27 <vup> maybe I don't see the obvious, but why not just put a small AsyncFIFO between the output of the SPIBus and the USB FIFO?

16:56 <gruetzkopf> that's most likely to be the more proper solution, true

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