ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<wens>
which one
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<geertu>
arnd: I doubt there are many m68k drivers that actually use readl() and friends.
<geertu>
Most were written using direct volatile pointer dereferences.
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<geertu>
Later, it was suggested to use readl(). Note that was before the convention that readl() is little endian.
<geertu>
Hence we are still stuck with a mess.
<geertu>
For romport ISA, you want to talk to Michael Schmitz. He knows the gory details.
<geertu>
Amiga PCMCIA only ever worked with a subset of NE2000 drivers, but people are still working on fixing that.
<arnd>
geertu: right, so the drivers in my list all seem to be for portable hardware with LE registers, so I guess they work fine with either CONFIG_ISA=n or when both ISA and Atari ROM are enabled, I have a path to fix that.
<arnd>
So they work regardless of whether ISA is enabled
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<arnd>
I also have patches for ne2000 with both Amiga pcmcia and Atari ROM to separate them from the ISA in/outb, which greatly simplifies the actual ISA stuff (q40)
<geertu>
arnd: Nothing is real ISA on m68k, except for Atari romport ISA (sort-of) and Q40
<arnd>
O had hoped to kill off GENERIC_IOMAP, but q40 still needs that
<geertu>
arnd: BTW, according to renesas.com, RZ/A1H will be available until 2031, so people may want XIP and running in only 10 MiB of on-chip RAM until beyond that...
<geertu>
RZ/G1H (8 GiB LPAE) is in production but "Not Recommended for New Designs", no final date listed
<arnd>
Ok, good to know. Do you know if the A1H works in XIP mode without extra patches now?
<geertu>
No idea.
<geertu>
(added checking this to my TODO list, you never know I ever get to it ;-)
<arnd>
I assume you also have no data on how many users actually have 8GiB on G1H, right? It only has a 2x32 bit wide DDR3 interface, so one would need eight 1GX8 chips, which makes it quite hard on cost, availability and board layout
<arnd>
I'm on my way to embeddedworld, will also check out the renesas (and TI) booths as well as memory manufacturers to see if they have data for that
<geertu>
No I don't have that info.
<geertu>
Enjoy EW!
<geertu>
My Lager (R-Car H2) has only 4 GiB, with 8 x MT41K512M8RH-125, which is obsolete and no longer manufactured accordign to Digi-Key
<geertu>
arnd: Make sure to inspect the Renesas boards near pinchartl ;-)
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<geertu>
arnd: People are still sending patches to arnd.bergmann@de.ibm.com...
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<bjdooks>
it would be nice if someone early on had put a device-tree,version property in and we could either warn or fixup if someone booted a newer kernel with an old dtb
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<ukleinek>
..ooOO(heretic! device trees are compatible in both directions!)
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<krzk>
There was also idea of versioning DTS for A/B testing. We also talked in context of arm64 laptops (T14s) what would be necessary to move DTB to firmware and still recognize some sort of changes, when firmware is updates.
<krzk>
/updates/updated/
<krzk>
but for such case I don't see the benefits - what kernel should do if you get old DTB? Add handling logic in each driver? What if you have 10 different old DTBs? big switch-case?
<bjdooks>
ukleinek: someone in tegra land made changes to the gpio port numbering, and now the ethernet reset driver is looking in the wrong gpio bank as they shoved 4 banks in hte middle
<bjdooks>
at lesat if they'd changed the gpio compatible i could match and change the translation
<bjdooks>
I'm starting to think I need to write "The Ben Dooks school of writing device trees good and doing versioning good too"
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<ukleinek>
uah
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* a3f
had the same though yesterday. The NFS export script didn't update the kernel/DT and I can just see the kernel hash in uname, but not a DT version..
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<geertu>
arnd: I can confirm I can configure and build a XIP kernel for RZ/A1H now, so there is progress. No idea if it works, though.
<geertu>
According to Chris XIP on RZ/A1 is dead. I have forwarded his full answer, which may help in prioritizing the removal of cruft ;-)
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<ukleinek>
a3f: the dtb contains a checksum
<wens>
arnd: my pull request seems to be stuck in my local host, which cannot connect to the kernel.org mail server right now :(
<ukleinek>
wens: you need a .msmtprc snippet?
<wens>
it's not the settings, it's the connections timing out for some reason
<wens>
probably network issues :(
<a3f>
ukleinek, oh, where? I see no mention of a built-in checksum in either dtc sources or in the deviccetree specification
<ukleinek>
hmm, I thought there was a checksum in the dtb header, but a quick look in the docs suggests I'm wrong
* ukleinek
had in mind that it's not possible to easily modify a dtb because of a crc32 (or similar) field.
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<a3f>
ukleinek, I seen discussion where "but DTB is signed" was used as an argument against fixing up some kinds of information into it. Maybe that's what you are remembering
<arnd>
I'm pretty sure the kernel checks the crc32 of the dtb very early during boot, just looked at that code recently. Not sure where how the CRC is stored
<geertu>
git grep -w of_fdt_crc32
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<ardb>
this is for /sys/firmware/fdt, which is supposed to expose the DT received from the firmware
<ardb>
so if the kernel modifies it, it will be flagged