ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<ukleinek>
broonie: operating an mcp23S17 behind an spi-imx controller, we see a performance benefit when the transfers of the used messages are binned into a single transfer.
<ukleinek>
broonie: I assume this isn't only true for the spi-imx driver and I wonder if it was sensible to introduce a layer between spi client drivers and spi bus drivers that "optimizes" messages
<ukleinek>
broonie: updating from 5.15 to 6.1 is quite a performance boost BTW. Testing repeating gpio bulk transfers, the time per transfer went down from 50...400 us to 14...31 us
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<broonie>
ukleinek: that'll be David Jander's work.
<broonie>
Concatenating transfers for performance is a bit interesting, ideally we'd be able to do it via scatter/gather lists over the message - ideally through scatter/gather if things are going to DMA.
<broonie>
For PIO it seems less likely to be exciting.
<ukleinek>
broonie: ack for David Jander
<ukleinek>
I didn't recheck, but I think the i.MX cannot do scatter/gather
<ukleinek>
(in the DMA engine that is)
<ukleinek>
broonie: is "a bit interesting" good, or too little to care in your eyes?
<broonie>
Good, but it's a bit of work. There's DMA controllers that can't do scatter gather and so on to worry about.
<ukleinek>
broonie: my idea is to add some logic to the spi core that (depending on the lowlevel driver) "flattens" the message to a single transfer.
<broonie>
Yes, but we really want to do that with a scatter/gather DMA rather than by linearising the buffers.
<ukleinek>
broonie: I don't follow, in general you cannot assume that the used DMA can do S/G?
<broonie>
Yes, that's why it's interesting.
<broonie>
But if you don't do that then for something like flash where you're doing large transfers you can end up spending so much time linearising the buffers that it's worse.
* ukleinek
nods
<broonie>
And it's just generally better. We probably need some limit on how big a buffer we linearise, and ideally just do scatter/gather where we can.
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<linusw__>
arnd: your DMA series gives a lot of interesting insight into what has been going on in cache design the recent 20 years... I don't understand half of it.
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