ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<HdkR>
Is there a branch of qemu somewhere that supports TME? Or am I SOL until hardware ships with it?
<ajb-linaro>
TME?
* ajb-linaro
looks it up
<HdkR>
Transactional Memory Extension
<ajb-linaro>
HdkR: yeah I'm not aware of any work in that area and I suspect it would be non-trivial to implement under TCG as well
* ajb-linaro
thought TME was v9 anyway
<HdkR>
I want to be prepared for the future and TME is a feature I can utilize
<HdkR>
Dang though
<ajb-linaro>
HdkR: what's the use case? I know cota had experimented with using Intel's transactional support in the backend during the development of MTTCG but other than that it seems to be a technology that didn't deliver on it's promises
<apritzel>
TME is indeed an optional v9.0 feature
<HdkR>
Memory safety when having loadstores cross a cacheline for me
<ajb-linaro>
HdkR: well the best place for all the latest greatest feature emulation is always going to be ARM's own models... but their team is much bigger than regular QEMU ARM contributor pool
<HdkR>
Of course
<HdkR>
I don't believe they have a model that supports it yet?
<HdkR>
Also usually sending an email to get access results in $$$ or nope :)
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<ajb-linaro>
HdkR: I'll let you into a secret, the QEMU team use the models to check a lot of it's behaviour - especially for ISA stuff
<HdkR>
Sounds reasonable. Just need a model that has the feature
<sudeepholla>
wwilly, clk_ddrc_freq is what I can see in the code, but I don't have that platform or even worked on it, so it is just a guess
<prabhakarlad>
maz: Oops my bad, patch has already landed in -next, I will send a fixes patch.
<sudeepholla>
prabhakarlad, do you use those in kernel ? I wonder what would happen to secure settings if OS can go and reset the GIC from the kernel(non-secure side)
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<sudeepholla>
prabhakarlad, same applies to power-domains and clocks too
<wwilly>
sudeepholla, yep, there is also a thing to control a bit on it in /sys/class/devfreq/ddr_devfreq/ running on a 4.9.78-147538-g244928755bbe, I think from a standard linaro tuto, I haven't install the board myself. do you know if the (last) mainline is well supported?
<sudeepholla>
wwilly, not sure what you mean by well supported ? All the merged features must be supported, if not you can report to the platform maintainer and get it fixed
<prabhakarlad>
sudeepholla: not used atm. For now its just being added to describe the HW.
<wwilly>
sudeepholla, ok, will try to get the board on my desk and install the mainline. meaning like all tweak from hisilicon to have the board running properly are merged, to have like cpu/gpu/ram dvfs, and a serial console running
<sudeepholla>
prabhakarlad, whats the point ? I mean I can't see a what to use them in OS. If firmware are using DT to discover GIC, makes sense, but I really doubt that too
<sudeepholla>
wwilly, since you mentioned u are running some Linaro thing, I mention to highlight the fact that there will be parity in features as Linaro might have all the in-flight patches and also hacks to get all the functionality working
<wwilly>
sudeepholla, ok great, will ask to get the board then. uhm, is the 960 have all the same hardware feature, but the NPU?
<sudeepholla>
wwilly, i have no idea sorry
<wwilly>
sudeepholla, no worries, thx
<maz>
prabhakarlad: hopefully this is only a DT patch, and not a kernel patch. I certainly don't intend to let anyone reset the GIC from within the kernel...
<prabhakarlad>
sudeepholla: do agree, I don't see the usecase as of now.
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<prabhakarlad>
maz: Yes just the DT patch (describing the HW).
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<sudeepholla>
prabhakarlad, I would say no usecase in future too IMO, if it is not used now, unlikely in future. I will be it to Rob, but I see no use in OS and no way to validate it.
<prabhakarlad>
+1
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<geertu>
marex: ofc we can, if we have access to the reset controller ;-)
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